Page History
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- ARM JTAG Connector (DS-5 D-Stream) J15 - PJTAG to EMIO multiplexing needed
- 12-pin IDC header socket J1 (right angle, max. VCCIO voltage 3.3V)
RJ45 GbE Connector
- SD Card Socket - Zynq SDIO0 Bootable bootable SD port
- 12-pin IDC header socket (right angle) J2
- Micro USB Connector J12 (Device, Host or OTG Modes)
- Battery holder for CR1220 (RTC backup voltage)
- 12-pin IDC header socket (vertical) J5
- 12-pin IDC header socket (vertical) J6
- User Push-Button S2 ("RESTART" button by default)
- User Push-Button S1 ("RESET" button by default)
- User LEDs D6, D7, D8, D9
- User LEDs D4, D5, D14, D15
- Mini USB Connector (USB JTAG and UART Interface) J7
- User 4-bit DIP-Switch S3
- User 4-bit DIP-Switch S4
- FTDI FT2232HQ USB 2.0 High Speed to UART/FIFO
- Lattice Semiconductor MachXO2 1200HC System Controller CPLD
- Jumper J4 to fix user button S2 to switched state
- 40-Pin-Header J13 for access to PL IO-bank-pins
- 40-Pin-Header J11 for access to PL IO-bank-pins
- Samtec Razor Beam™ LSHM-150 B2B connector JB1
- Samtec Razor Beam™ LSHM-150 B2B connector JB2
- Samtec Razor Beam™ LSHM-130 B2B connector JB3
- Barrel jack for 12V power supply J10
- Jumper J21 to select supply voltage of VIOTB
- Jumper J9, J19, J20 to select supply voltage of USB-VBUS
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| Note |
|---|
| Warning: When using FTDI software tools, the 256-byte user EEPROM can be erased without confirmation. As a consequence, the Digilent license stored in that the EEPROM will also be deleted. |
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- J7 as mini-USB connector wired to on-board FTDI FT2232HQ FT2232H chip.
- J12 as micro-USB connector wired to B2B connector JB3 (usually there is an USB transceiver on the SoM).
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JTAG access to the CPLD and SoM is provided via mini-USB JTAG interface J7 (FTDI FT2232H) and controlled by DIP switch S3-3. To enable JTAG port of the CPLD, set switch S3-3 JTAGEN to OFF.
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There are eight LEDs (D6, D7, D8, D9, D4, D5, D14, D15) available to the user. All LEDs are red colored and mapped to the on-board System Controller CPLD. Their functions are programmable and depend on the firmware of the System Controller CPLD. For detailed information, please refer to the documentation of the TE0705 System Controller CPLD.
One green Green LED D22 shows the is to indicate availability of the 3.3V power supply voltage of to the TE0705 Carrier Board.
4-bit DIP-switch S3
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carrier board.
4-bit DIP-switch S3
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| Switch | Functionality |
|---|---|
| S3-1 | CM1: Mode pin 1 (routed to Carrier System Controller CPLD). |
| S3-2 | CM0: Mode pin 0 (routed to Carrier System Controller CPLD). |
| S3-3 | JTAGEN: Set to ON for normal JTAG operation. Must be moved to OFF position for TE0705 System Controller CPLD update only. |
| S3-4 | MIO0: Set MIO0 - pin (on MIO0-Bank) on Zynq - modules, else active-low -active user IO - pin. |
Table 1: Configuration of DIP-switch S3.
4-bit DIP-switch S4
Additionally , on the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (16) in Figure 1) available. The signals of the switch are routed to carrier board's System Controller CPLD and are fully user-configurable depending on a customer developed S4 available routed to the System Controller CPLD which function is user configurable via custom CPLD firmware. Please refer to the documentation of the TE0705 System Controller CPLD to get information how to put these user-switches in operation. documentation for more information.
All switch S4 pins The switches are connected to 3.3V pull-up resistors and have a physical high-level of 3.3V on OFF-in OFF position.
User
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Push-Buttons
On the TE0705 Carrier Board there are two push buttons (S1 and S2) and are routed to the System Controller CPLD and available to the user. The default mapping of the push buttons is as follows:
| Name | Default Mapping: | ||
|---|---|---|---|
| S1 | If S1 is pushed, the active-low RESet IN (RESIN) signal will be asserted. Note: This reset can also be forced by the FTDI USB to JTAG interface. | ||
| S2 | If S2 is pushed, the active-high Power ON (PON) signal (that is internally pulled-up) will be deasserted, which can be considered as a "RESTART" button to switch off (push button) and on (release button) all on-module power supplies (except 3.3VIN). Note: The capability of the switch to be enabled the first time will become active shortly after Power on Reset (POR).
By closing jumper J4, the PON signal will be permanently deasserted, hence the power FET switch and the DC-DC converters on module will be disabled. |
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IDC header J1 provides access to SoM's PL IO-bank pins, whereby 6 pins (net name: 'MIO10' to 'MIO15') of this header are also routed to the System Controller CPLD.
If Zynq - module is mounted on the TE0705 carrier board, the pins of this header are routed to the corresponding pins of the PS logic of the SoM: MIO0-bank pins MIO0, MIO9-MIO15 are accessible on header J1 and operable with max. VCCIO voltage 3.3V.
An exception here is the 'MIO12'-pin, which is buffered with a Schmitt-Trigger -Buffer buffer with a hystersis hysteresis of 5.0V.
IDC header socket J2
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operable with fixed (3.3V) or adjustable IO-voltage VIOTB (not usable as LVDS pairs, only single-ended IOs).
Power and Power-On Sequence
Power Supply
Power Single 12V power supply with minimum current capability of 3A at 12V for system startup is recommended to operate the board.
Power-On Sequence
The on-board voltages of the carrier board will be powered up simultaneously after one single power-supply with a nominal voltage of 12V is connected to the power-jack J10.
The PL IO-bank supply voltage FMC_VADJ will be is available after the output of the 5.0V DC-DCDC-DC converter is active and the pin EN_FMC pin of the SC-System Controller CPLD is asserted.
Figure 3: Power-Up On sequence diagram.
Configuring VCCIO
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There is the possibility to select the module's PL IO-bank's supply voltage VIOTB to fixed adjustable voltages FMC_VADJ. Therefore, the jumper J21 has to be set to the position 1, 2-3, to connect the pins 'VIOTB' and 'ADJ'. On position 1-2, 3, the supply voltage VIOTB will be fixed to 3.3V
Table 3 shows the switch-configuration of the DIP-switch S3 to set the voltage FMC_VADJ.
Note: The configuration of FMC_VADJ depends on the used firmware of the System Controller CPLD. For detailed information, refer to the documentation of the TE0705 System Controller CPLD.
S3-1 (CM1) | S3-2 (CM2) | FMC_VADJ Value |
|---|---|---|
OFF | OFF | 1.8V |
OFF | ON | 2.5V |
ON | OFF | 3.3V |
ON | ON | 1.8V (Note: Also SoM's SC-CPLD JTAG-access is enabled, see section JTAG in the documentation of the TE0705 System Controller CPLD.) |
Table 3: Switch S3 positions for fixed values of the FMC_VADJ voltage
Configuring Power Supply of the Micro USB Connector (Device, Host or OTG Modes)
The TE0705 carrier board can be configured as a USB host device. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the over-current logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY on the mounted SoM. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).
Additionally, the TE0705 carrier board is equipped with a second mini USB port J7 that is connected to a "USB to multi-purpose UART/FIFO IC" from FTDI (FT2232HQ) and provides a USB-to-JTAG interface between a host PC and the TE0705 carrier board and the mounted SoM, respectively. Because it acts as a USB function device, no power switch is required (and only a ESD protection must be provided) in this case.
Summary of VCCIO
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Configuration
All B2B VCCIO supply voltages to On the TE0705 carrier board all PL IO-bank's supply voltages of the 4 x 5 SoM (VCCIOA, VCCIOB, VCCIOC and VCCIOD, VCCIOD; see 4 x 5 Module Integration Guide) are connected to the VCCIO voltage 3.3V VIOTB, which is either fixed to 3.3V (J21: 1-2, 3) or selectable with the adjustable supply-voltage FMC_VADJ (J21: 1, 2-3). The supply-voltages have following pin assignments on B2B-connectors:
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| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
| Vin VIN supply voltage | 11.4 | 12.6 | V | - |
Physical Dimensions
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All dimensions are given in millimeters.
Figure 4: Physical dimensions of the TE0705-04 carrier board.
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| Date | Revision | Notes | PCN | Documentation link |
|---|---|---|---|---|
| 2016-10-04 | 04 | |||
| - | 03 | |||
| - | 02 | |||
| - | 01 |
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Figure 5: Hardware revision number.
Hardware revision number is printed on the PCB board next to the model number separated by the dash.
Document Change History
| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-02-09 | Ali Naseri, Jan Kumann | TRM for TE0705-04 | |
| 2017-01-15 | 0.1 | Ali Naseri | Initial document. |
Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| 2016-10-04 | 04 | |||
| - | 03 | |||
| - | 02 | |||
| - | 01 |
Disclaimer
| Include Page | ||||
|---|---|---|---|---|
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