Page History
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Term | Description |
---|---|
Adapter Board | Adapts the Reference Motor to the EDPS Board. |
Control Board | An electronic board for controlling the EDPS Board; the EDDP Kit uses Digilent , a Digilent board Arty Z7 for that purpose. |
EDDP | Electronic Drive Development Platform. |
EDDP Kit | A kit consisting of the EDPS Board, the Reference Motor, the Adapter board and. |
EDPS Board | An Electric Drive Power Stage Board, the EDDP Kit contains a Trenz Electronic GmbH board TEC0053 to be used as an EDPS Board. |
Host PC | A computer capable of running a web browser in order to run the Web UI. |
Reference Motor | The motor included in the EDDP Kit. This motor is of brushless type and is already mated with an encoder. |
Web UI | A user interface in the form of a web page permitting operating the EDDP. |
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Figure 15: Block diagram of the EDDP.
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List of additional documents
FPGA resources utilization
An excerpt of the FPGA resource utilization by the FOC SDSoC Application Project is shown in the Table 2. The FPGA used on the Controller Board is Xilinx 7z010clg400-1.
The power draw of the design is about 220mW as measured by the increase of the power draw of the Control Board after configuring the FPGA.
Type | Used | Available | Util% |
---|---|---|---|
Slice LUTs | 5758 | 17600 | 32.72 |
Slice Registers | 7277 | 35200 | 20.67 |
F7 Muxes | 33 | 8800 | 0.38 |
RAMB36/FIFO | 21 | 60 | 35 |
RAMB18 | 4 | 120 | 3.33 |
DSP48E1 | 34 | 80 | 42.50 |
BUFGCTRL | 4 | 32 | 12.50 |
MMCME2_ADV | 1 | 2 | 50 |
Table 2: FPGA resources utilization.
List of additional documents
The additional documents, listed in the Table 3, can be downloaded from The additional documents, listed in the Table 2, can be downloaded from Trenz EDDP Web Hub:
Title | Description |
---|---|
FOC SDSoC | Implementation of a Field-Oriented Control algorithm in C++ with Vivado SDSoC |
SDSoC Hardware Platform ARTY-Z7 | A basis for building Vivado SDSoC applications running on an Arty-Z7 board connected to a TEC0053 board |
AXI4-Stream AD7403 | An IP core for filtering the delta-sigma bitstream read from one or more ADC-s of type of AD7403 to an AXI4-Stream of samples |
AXI4-Stream Encoder | An IP core for converting impulses from a relative index encoder with an index signal to an AXI4-Stream of position and speed data |
AXI4-Stream PWM | An IP core for generating PWM signals according to the input AXI4-Stream |
AXI4-Stream Concat | An IP core for concatenating AXI4-Streams |
Web GUI | A Web UI to control and monitor an EDPS Board over the Network API |
Network API | A communication protocol, based on Websockets, to control an EDPS board |
Embedded Linux Code | A server program interfacing to an EDPS board and implementing the Network API and the functions of a Web Server |
Table 23: List of additional documents.
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Date | Revision | Contributors | Description | ||||||||
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| Jan Kumann | General formatting changes and small corrections. | |||||||||
2017-08-14 | v.10 | Antti Lukats, Andrei Errapart | Initial document. |
Table 24: Document change history.
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