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Table of Contents

Table of Contents

Overview

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Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0808" for downloadable version of this manual and the rest of available documentation.
 

The Trenz Electronic TE0808 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+ MPSoC, max. 8 GByte up to 8 GBytes of DDR4 SDRAM with via 64-Bit width databus connectionbit wide data bus, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is Os are provided via rugged high-speed stacking connections. All this in a compact 5.2 x 7.6 cm form factor, at the most competitive price.


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Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.
Note
Important Information for TE0808 boards which are equipped with ES1 or ES2 silicon: Erratas and functional restrictions may exist, please check Xilinx documentation and contact your local Xilinx FAE for restrictions.
Key Features
  • MPSoC: ZYNQ UltraScale+ ZU9EG 900 pin package
  • Memory
    - 64-Bit DDR4, 8 GByte maximum
    - Dual SPI boot Flash in parallel, 512 MByte maximum
  • User I/OOs
    - 65 x MIOPS MIOs, 48 x PL HD (all)GPIOs,  156 x PL HP GPIOs (3 banks)
    - Serial transceivertransceivers: 4 x GTR + 16 x GTH
    - Transceiver clocks inputs and outputs
    - PLL clock generator inputs and outputs
  • Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
  • B2B connectors: 4 x 160 pin
  • Si5345 - 10 Si5345 - 10 output PLL
  • All power supplies on board, single 3.3V power source required
    - 14 on-board DC-DC regulators and 13 LDOs
    - LP, FP, PL separately controlled power domains
  • Support for all boot modes (except NAND) and scenarios
  • Support for any combination of PS connected peripherals
  • Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
  • B2B connectors: 4 x 160 pin
Block Diagram
Figure 1: TE0808-04 Block Diagram.
...
  1. Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
  2. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
  3. Red LED (DONE), D1
  4. 256Mx16 DDR4-2400 SDRAM, U12
  5. 256Mx16 DDR4-2400 SDRAM, U9
  6. 256Mx16 DDR4-2400 SDRAM, U2
  7. 256Mx16 DDR4-2400 SDRAM, U3
  8. 12A PowerSoC DCDC DC-DC converter, U4
  9. Quartz crystal, Y1
  10. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
  11. 10-channel programmable PLL clock generator, U5
  12. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  13. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  16. Quartz crystal, Y2
  17. 256 Mbit serial NOR Flash memory, U7
  18. 256 Mbit serial NOR Flash memory, U17
...
Each connector has a specific arrangement of the signal pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq UltrascaleUltraScale+ MPSoC like I/O - banks, interfaces and Gigabit transceivers
or to the on-board peripherals.
...
BankTypeB2B ConnectorSchematic Names / Connector PinsI/O Signal CountSignalsLVDS Pairs CountVCCO Bank VoltageNotes
47HDJ3
B47_L1_P ... B47_L12_P
B47_L1_N ... B47_L12_N
24 I/O'sOs12
VCCO47
pins J3-43, J3-44
VCCO max. 3.3V
usable as single-ended I/O'sOs
48HDJ3
B48_L1_P ... B48_L12_P
B48_L1_N ... B48_L12_N
24 I/O'sOs12
VCCO48
pins J3-15, J3-16
VCCO max. 3.3V
usable as single-ended I/O'sOs
64HPJ4
B64_L1_P ... B64_L24_P
B64_L1_N ... B64_L24_N
B_64_T0 ... B_64_T3
52 I/O's24
VCCO64
pins J4-58, J4-106
VCCO max. 1.8V
usable as single-ended I/O'sOs
65HPJ4
B65_L1_P ... B65_L24_P
B65_L1_N ... B65_L24_N
B_65_T0 ... B_65_T3
52 I/O'sOs24
VCCO65
pins J4-69, J4-105
VCCO max. 1.8V
usable as single-ended I/O'sOs
66HPJ1
B66_L1_P ... B66_L24_P
B66_L1_N ... B66_L24_N
B_66_T0 ... B_66_T3
48 I/O'sOs24
VCCO66
pins J1-90, J1-120
VCCO max. 1.8V
usable as single-ended I/O'sOs
500MIOJ3MIO13 ... MIO2513 I/O'sOs-PS_1V8user User configurable I/O's Os on B2B
501MIOJ3MIO26 ... MIO5126 I/O'sOs-PS_1V8user User configurable I/O's Os on B2B
502MIOJ3MIO52 ... MIO7726 I/O'sOs-PS_1V8user User configurable I/O's Os on B2B
Table 2: B2B connector pin-outs of available PL and PS banks of the TE0808-04 SoM. 

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.
...
BankTypeB2B ConnectorCount of MGT LanesSchematic Names / Connector PinsMGT Bank's Reference Clock Inputs
228GTHJ1
4 GTH lanes
(4 RX / 4 TX)
B228_RX3_P, B228_RX3_N, pins J1-2751, J1-2953
B228_TX3_P, B228_TX3_N, pins J1-2650, J1-2852
B228_RX2_P, B228_RX2_N, pins J1-3357, J1-3559
B228_TX2_P, B228_TX2_N, pins J1-3256, J1-3458
B228_RX1_P, B228_RX1_N, pins J1-3963, J1-4165
B228_TX1_P, B228_TX1_N, pins J1-3862, J1-4063
B228_RX0_P, B228_RX0_N, pins J1-4569, J1-4771
B228_TX0_P, B228_TX0_N, pins J1-4468, J1-4670
1 reference clock signal (B228_CLK0) from B2B connector
J3 (pins J3-60, J3-62) to bank's pins R8/R7
1 reference clock signal (B228_CLK1) from programmable
PLL clock generator U5 to bank's pins N8/N7
229GTHJ1
4 GTH lanes
(4 RX / 4 TX)
B229_RX3_P, B229_RX3_N, pins J1-27, J1-29
B229_TX3_P, B229_TX3_N, pins J1-26, J1-28
B229_RX2_P, B229_RX2_N, pins J1-33, J1-35
B229_TX2_P, B229_TX2_N, pins J1-32, J1-34
B229_RX1_P, B229_RX1_N, pins J1-39, J1-41
B229_TX1_P, B229_TX1_N, pins J1-38, J1-40
B229_RX0_P, B229_RX0_N, pins J1-45, J1-47
B229_TX0_P, B229_TX0_N, pins J1-44, J1-46
1 reference clock signal (B229_CLK0) from B2B connector
J3 (pins J3-65, J3-67) to bank's pins L8/L7
1 reference clock signal (B229_CLK1) from programmable
PLL clock generator U5 to bank's pins J8/J7
230GTHJ1
4 GTH lanes
(4 RX / 4 TX)
B230_RX3_P, B230_RX3_N, pins J1-3, J1-5
B230_TX3_P, B230_TX3_N, pins J1-2, J1-4
B230_RX2_P, B230_RX2_N, pins J1-9, J1-11
B230_TX2_P, B230_TX2_N, pins J1-8, J1-10
B230_RX1_P, B230_RX1_N, pins J1-15, J1-17
B230_TX1_P, B230_TX1_N, pins J1-14, J1-16
B230_RX0_P, B230_RX0_N, pins J1-21, J1-23
B230_TX0_P, B230_TX0_N, pins J1-20, J1-22
1 reference clock signal (B230_CLK1) from B2B connector
J3 (pins J3-59, J3-61) to bank's pins G8E8/G7E7
1 reference clock signal (B230_CLK0) from programmable
PLL clock generator U5 to bank's pins E8G8/E7G7
128GTHJ2
4 GTH lanes
(4 RX / 4 TX)
B128_RX3_N, B128_RX3_P, pins J2-28, J2-30
B128_TX3_N, B128_TX3_P, pins J2-25, J2-27
B128_RX2_N, B128_RX2_P, pins J2-34, J2-36
B128_TX2_N, B128_TX2_P, pins J2-31, J2-33
B128_RX1_N, B128_RX1_P, pins J2-40, J2-42
B128_TX1_N, B128_TX1_P, pins J2-37, J2-39
B128_RX0_N, B128_RX0_P, pins J2-46, J2-48
B128_TX0_N, B128_TX0_P, pins J2-43, J2-45
1 reference clock signal (B128_CLK1) from B2B connector
J2 (pins J2-22, J2-24) to bank's pins D25/D26
1 reference clock signal (B128_CLK0) from programmable
PLL clock generator U5 to bank's pins F25/F26
505GTRJ2
4 GTR lanes
(4 RX / 4 TX)
B505_RX3_N, B505_RX3_P, pins J2-52, J2-54
B505_TX3_N, B505_TX3_P, pins J2-49, J2-51
B505_RX2_N, B505_RX2_P, pins J2-58, J2-60
B505_TX2_N, B505_TX2_P, pins J2-55, J2-57
B505_RX1_N, B505_RX1_P, pins J2-64, J2-66
B505_TX1_N, B505_TX1_P, pins J2-61, J2-63
B505_RX0_N, B505_RX0_P, pins J2-70, J2-72
B505_TX0_N, B505_TX0_P, pins J2-67, J2-69
2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector
J2 (pins J2-10/J2-12, J2-16/J2-18) to bank's pins P25/P26, M25/M26
2 reference clock signal (B505_CLK2, B505_CLK3) from programmable
PLL clock generator U5 to bank's pins K25/K26, H25/H26
...
JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage ' PS_1V8'.
JTAG SignalB2B Connector Pin
TCKJ2-120
TDIJ2-122
TDOJ2-124
TMSJ2-126
...
The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B - connector J2.
For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.
SignalB2B Connector PinFunction
DONEJ2-116PL configuration completed.
PROG_BJ2-100PL configuration reset signal.
INIT_BJ2-98PS is initialized after a power-on reset.
SRST_BJ2-96System reset.
MODE0 ... MODE3J2-109/J2-107/J2-105/J2-103
4-bit boot mode pins.
For further information about the boot - modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM 
 section 'Boot and Configuration'.
ERR_STATUS / ERR_OUTJ2-86 / J2-88
ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU)-.
ERR_STATUS indicates a secure lock-down state.
PUDC_BJ2-127Pull-up during configuration (pulled-up to PL_1V8).
...
Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
     
MIOSignal Schematic NameU7 Pin 
MIOSignal Schematic NameU17 Pin
0SPI Flash -SCK/M4CLKB2
7SPI Flash -SCKCS
C2
1SPI Flash -DQ1/M1IO1
D2
8SPI Flash -DQ0/M0IO0
D3
2SPI Flash -DQ2/M2IO2
C4
9SPI Flash -DQ1/M1IO1
D2
3SPI Flash -DQ3/M3IO3D4 
10SPI Flash -DQ2/M2IO2
C4
4SPI Flash -DQ0/M0IO0
D3
11SPI Flash -DQ3/M3IO3D4
5SPI Flash -SCKCS
C2
12SPI Flash -SCK/M4CLK
B2
Table 7: PS MIO pin assignment of the Quad SPI Flash memory ICs.
Boot Process
The boot source device and mode of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins, which generate a 4-bit code to select the boot mode. The pins are accessible on B2B connector J2:
...
Table 8: Boot mode pins on B2B connector J2.

Following boot modes are possible on the TE0808 UltraScale+ module by generating the corresponding 4-bit code by the pins ' PS_MODE0 ' ... ' PS_MODE3 ' (little-endian alignment):
...
For functional details see  ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).
...
The TE0808-04 SoM is equipped with with four DDR4-2400 SDRAM modules chip with up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64-bit data bus.
Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.
Programmable PLL Clock Generator
...
InputConnected toFrequencyNotes
IN0On-board Oscillator (U25)25.000000 MHz-
IN1B2B Connector pins J2-34, J2-1 6 (differential pair)UserAC decoupling required on base
IN2B2B Connector pins J3-66, J3-68 (differential pair)UserAC decoupling required on base
IN3OUT9UserLoop-back from OUT9
OutputConnected toFrequencyNotes
OUT0B2B Connector pins J2-3, J2-1 (differential pair)UserDefault off
OUT1B230 CLK0UserDefault off
OUT2B229 CLK1UserDefault off
OUT3B228 CLK1UserDefault off
OUT4B505 CLK2UserDefault off
OUT5B505 CLK3UserDefault off
OUT6B128 CLK0UserDefault off
OUT7B2B Connector pins J2-713, J2-9 15 (differential pair)UserDefault off
OUT8B2B Connector pins J2-137, J2-15 9 (differential pair)UserDefault off
OUT9IN3 (Loop-back)UserDefault off
XA/XBQuartz (Y1)50.000 MHz-
Table 11: Programmable PLL clock generator input/output. 

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.
SignalB2B Connector PinFunction
PLL_FINCJ2-81Frequency increment.
PLL_LOLNJ2-85Loss of lock (active-low).
PLL_SEL0 / PLL_SEL1J2-93 / J2-87Manual input switching.
PLL_FDECJ2-94Frequency decrement.
PLL_RSTJ2-5989
Device reset (active-low)
PLL_SCL / PLL_SDAJ2-90 / J2-92
I2C interface, external pull-ups needed for SCL / SDA lines.
I2C address in current configuration: 1101000b1101001b.
Table 12: B2B connector pin-out of Si5345A programmable clock generator.
...
Figure 3: Power Distribution Diagram.
 Note
Current rating of  Samtec Razor Beam™ LSHMBeam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 21.0A 5 A per pin (2 adjacent pins powered1 pin powered per row).
Power-On Sequence Diagram
...
     
Enable-SignalB2B Connector PinMax. VoltageNote
Power-Good-SignalB2B Connector PinPull-up ResistorNote
EN_LPDJ2-1086VTPS82085SIL data sheet 
LP_GOODJ2-1064K7, pulled up to LP_DCDC-
EN_FPDJ2-102DCDCINNC7S08P5X data sheet 
PG_FPDJ2-1104K7, pulled up to DCDCIN-
EN_PLJ2-101PL_DCINleft floating for logic high
(drive to GND for logic low)		 
PG_PLJ2-104External pull-up needed (max. voltage GT_DCDC),
max. sink current 1 mA		4K7, pulled up to PL_DCIN
TPS82085SIL /TPS82085SIL /
NC7S08P5X data sheet
EN_DDRJ2-112DCDCINNC7S08P5X data sheet
PG_DDRJ2-1144K7, pulled up to DCDCIN-
EN_PSGTJ2-84DCDCINNC7S08P5X data sheet
PG_PSGTJ2-82External pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74801 data sheet
EN_GT_RJ2-95GT_DCDCNC7S08P5X data sheet 
PG_GT_RJ2-91External pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74401 data sheet
EN_GT_LJ2-79GT_DCDCNC7S08P5X data sheet
PG_GT_LJ2-97External pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74801 data sheet
EN_PLL_PWRJ2-776VTPS82085SIL data sheet
PG_PLL_1V8J2-80External pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS82085SIL data sheet
...
Power Rail Name
B2B J1 PinsB2B J2 PinsB2B J3 Pins
Directions
Note
PL_DCIN151, 153, 155, 157, 159--Input-
DCDCIN
-
154, 156, 158, 160,
153, 155, 157, 159
-Input-
LP_DCDC-138, 140, 142, 144-Input-
PS_BATT-125-Input-
GT_DCDC--157, 158, 159, 160Input-
PLL_3V3--152InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--151OutputInternal voltage level
1.8V nominal output
PS_1V8-99147, 148Output
Internal voltage level
1.8V nominal output
PL_1V891, 121--Output
Internal voltage level
1.8V nominal output
DDR_1V2-135-Output
Internal voltage level
1.2V nominal output
...
B2B connectors
 Include Page
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B ConnectorsIN:SS5-ST5 connectorsIN:SS5-ST5 connectors
Variants Currently In Production
2IB2FFVC900I
Module VariantZynq UltraScale+ MPSoCDDR4Junction TemperatureOperating Temperature Range
TE0808-04-09EG-1EAXCZU9EG-1FFVC900E2GB0°C - 100°CExtended Temperature Range
TE0808-04-09EG-1EBXCZU9EG-1FFVC900E4GB0°C - 40°C - 100°CIndustrial Extended Temperature Range
...
TE0808-04
...
-09EG-1ED(1)XCZU9EG-1FFVC900E4GB0°C - 100°CExtended Temperature Range
TE0808-04-09EG-2IBXCZU9EG-2FFVC900I4GB-40°C - 100°CIndustrial Temperature Range
(1) Note: Lower B2B connector profile,check distance bolt of between module and carrier
Table 19: Differences between variants of Module TE0808-04
Technical Specifications
Absolute Maximum Ratings
Technical Specifications
Absolute Maximum Ratings
Parameter
MinMax
Unit
Notes / Reference Document
PL_DCIN-0.374VTPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG
DCDCIN-0.374VTPS82085SIL / TPS51206 data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.374VTPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
PS_BATT-0.52VXilinx DS925 data sheet
PLL_3V3-0.53.8VSi5345/44/42 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
VREF-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage
-0.51.2VXilinx DS925 data sheet
Voltage on input pins of
NC7S08P5X 2-Input AND Gate
-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC
Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41
-0.3VDD + 0.3V
TPS3106 data sheet,
VDD = LP_DCDC
"Enable"-signals on TPS82085SIL
(EN_PLL_PWR, EN_LPD)		-0.37VTPS82085SIL data sheet
Storage temperature (ambient)
-40
100
°C
ROHM Semiconductor SML-P11 Series data sheet
...
ParameterMinMaxUnitNotes / Reference Document
PL_DCIN23.533.6V
EN63A0QI / TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
DCDCIN3.133.6VTPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC23.533.6VTPS82085SIL / TPS3106 TPS3106K33DBVR data sheet
GT_DCDC23.533.6VTPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT1.21.5VXilinx DS925 data sheet
PLL_3V33.143.47VSi5345/44/42 data sheet
3.3V typical
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Voltage on input pins of
NC7S08P5X 2-Input AND Gate		0VCCV
NC7S08P5X data sheet,
see schematic for VCC
Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41
0VDDV
TPS3106 data sheet,
VDD = LP_DCDC
...
  • Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers
  • Mating height with standard connectors: 4mm5mm
  • PCB thickness: 1.6mm
  • Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
...
 DateRevision
Notes
Link to PCNDocumentation Link
-04First production silicon-TE0808-04
-03Second ES production release-TE0808-03
2016-03-0902First ES production release-TE0808-02
-01Prototypes--
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Image Removed
Document Change History
the dash.
Image Added
Document Change History
v.13V1
 Date
Revision
ContributorsDescription
 Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat
 Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat
 Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat
  • typo DDR section
2022-09-13
v.41
Vadim Yunitski 
  • Updated PG_PL pull-up resistor requirements
2021-09-07V.39John Hartfiel
  • Correction Power section
2021-05-17v.37John Hartfiel
  • typo correction in DDR section
2021-03-11v.35Antti Lukats
  • typo correction in PLL_RST
  • add pin on power rails table
  • correction MGT Lane assignment
  • correction MGT CLK assignment
2019-01-27
v.30Martin Rohrmüller 
  • Corrected clock connection to J2
2018-11-20
v.29
John Hartfiel
  • Notes for power supply
2018-08-27
v.27John Hartfiel
  • typo correction SI5345 I2C address
2028-06-28
v.26John Hartfiel
  • typo SI5348 B2B IOs + link correction
2017-11-13
v.24Ali Naseri
  • updated B2B connector max. current rating per pin
2017-11-13

v.22

John Hartfiel
  • rework B2B section
2017-10-20
v.21
Ali Naseri
  • Update links (pdf, documentation) to revision 4
  • ES silicon note removed
2017-08-28
v.15
John Hartfiel
  • Update section: Variants Currently In Production
2017-08-28v.14
 Date
Revision
ContributorsDescription
 Page info
modified-datemodified-date
dateFormatyyyy-MM-dd
Jan Kumann
  • Block diagram changed.
  • SPI flash section fixed.
  • Few smaller improvements.
2017-08-15v.12Vitali TsiukalaChanged signals count in the B2B connectors table
2017-08-15
v.11
John Hartfiel, Ali Naseri
  • PCB REV04 Initial release
  • update boot mode section
2017-02-06v.1Jan KumannInitial document
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