Page History

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Bank	Type	B2B Connector	Count of MGT Lanes	Schematic Names / Connector Pins	MGT Bank's Reference Clock Inputs
228	GTH	J1	4 GTH lanes (4 RX / 4 TX)	B228_RX3_P, B228_RX3_N, pins J1-51, J1-53 B228_TX3_P, B228_TX3_N, pins J1-50, J1-52 B228_RX2_P, B228_RX2_N, pins J1-57, J1-59 B228_TX2_P, B228_TX2_N, pins J1-56, J1-58 B228_RX1_P, B228_RX1_N, pins J1-63, J1-65 B228_TX1_P, B228_TX1_N, pins J1-62, J1-63 B228_RX0_P, B228_RX0_N, pins J1-69, J1-71 B228_TX0_P, B228_TX0_N, pins J1-68, J1-70	1 reference clock signal (B228_CLK0) from B2B connector J3 (pins J3-60, J3-62) to bank's pins R8/R7 1 reference clock signal (B228_CLK1) from programmable PLL clock generator U5 to bank's pins N8/N7
229	GTH	J1	4 GTH lanes (4 RX / 4 TX)	B229_RX3_P, B229_RX3_N, pins J1-27, J1-29 B229_TX3_P, B229_TX3_N, pins J1-26, J1-28 B229_RX2_P, B229_RX2_N, pins J1-33, J1-35 B229_TX2_P, B229_TX2_N, pins J1-32, J1-34 B229_RX1_P, B229_RX1_N, pins J1-39, J1-41 B229_TX1_P, B229_TX1_N, pins J1-38, J1-40 B229_RX0_P, B229_RX0_N, pins J1-45, J1-47 B229_TX0_P, B229_TX0_N, pins J1-44, J1-46	1 reference clock signal (B229_CLK0) from B2B connector J3 (pins J3-65, J3-67) to bank's pins L8/L7 1 reference clock signal (B229_CLK1) from programmable PLL clock generator U5 to bank's pins J8/J7
230	GTH	J1	4 GTH lanes (4 RX / 4 TX)	B230_RX3_P, B230_RX3_N, pins J1-3, J1-5 B230_TX3_P, B230_TX3_N, pins J1-2, J1-4 B230_RX2_P, B230_RX2_N, pins J1-9, J1-11 B230_TX2_P, B230_TX2_N, pins J1-8, J1-10 B230_RX1_P, B230_RX1_N, pins J1-15, J1-17 B230_TX1_P, B230_TX1_N, pins J1-14, J1-16 B230_RX0_P, B230_RX0_N, pins J1-21, J1-23 B230_TX0_P, B230_TX0_N, pins J1-20, J1-22	1 reference clock signal (B230_CLK1) from B2B connector J3 (pins J3-59, J3-61) to bank's pins G8E8/G7E7 1 reference clock signal (B230_CLK0) from programmable PLL clock generator U5 to bank's pins E8G8/E7G7
128	GTH	J2	4 GTH lanes (4 RX / 4 TX)	B128_RX3_N, B128_RX3_P, pins J2-28, J2-30 B128_TX3_N, B128_TX3_P, pins J2-25, J2-27 B128_RX2_N, B128_RX2_P, pins J2-34, J2-36 B128_TX2_N, B128_TX2_P, pins J2-31, J2-33 B128_RX1_N, B128_RX1_P, pins J2-40, J2-42 B128_TX1_N, B128_TX1_P, pins J2-37, J2-39 B128_RX0_N, B128_RX0_P, pins J2-46, J2-48 B128_TX0_N, B128_TX0_P, pins J2-43, J2-45	1 reference clock signal (B128_CLK1) from B2B connector J2 (pins J2-22, J2-24) to bank's pins D25/D26 1 reference clock signal (B128_CLK0) from programmable PLL clock generator U5 to bank's pins F25/F26
505	GTR	J2	4 GTR lanes (4 RX / 4 TX)	B505_RX3_N, B505_RX3_P, pins J2-52, J2-54 B505_TX3_N, B505_TX3_P, pins J2-49, J2-51 B505_RX2_N, B505_RX2_P, pins J2-58, J2-60 B505_TX2_N, B505_TX2_P, pins J2-55, J2-57 B505_RX1_N, B505_RX1_P, pins J2-64, J2-66 B505_TX1_N, B505_TX1_P, pins J2-61, J2-63 B505_RX0_N, B505_RX0_P, pins J2-70, J2-72 B505_TX0_N, B505_TX0_P, pins J2-67, J2-69	2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector J2 (pins J2-10/J2-12, J2-16/J2-18) to bank's pins P25/P26, M25/M26 2 reference clock signal (B505_CLK2, B505_CLK3) from programmable PLL clock generator U5 to bank's pins K25/K26, H25/H26

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The TE0808-04 SoM is equipped with with four DDR4-2400 SDRAM modules chip with up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64-bit data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

Programmable PLL Clock Generator

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Enable-Signal	B2B Connector Pin	Max. Voltage	Note	Power-Good-Signal	B2B Connector Pin	Pull-up Resistor	Note
EN_LPD	J2-108	6V	TPS82085SIL data sheet	LP_GOOD	J2-106	4K7, pulled up to LP_DCDC	-
EN_FPD	J2-102	DCDCIN	NC7S08P5X data sheet	PG_FPD	J2-110	4K7, pulled up to DCDCIN	-
EN_PL	J2-101	PL_DCIN	left floating for logic high (drive to GND for logic low)	PG_PL	J2-104External pull-up needed (max. voltage GT_DCDC), max. sink current	1 mA4K7, pulled up to PL_DCIN	TPS82085SIL / NC7S08P5X data sheet
EN_DDR	J2-112	DCDCIN	NC7S08P5X data sheet	PG_DDR	J2-114	4K7, pulled up to DCDCIN	-
EN_PSGT	J2-84	DCDCIN	NC7S08P5X data sheet	PG_PSGT	J2-82	External pull-up needed (max. 5.5V), max. sink current 1 mA	TPS74801 data sheet
EN_GT_R	J2-95	GT_DCDC	NC7S08P5X data sheet	PG_GT_R	J2-91	External pull-up needed (max. 5.5V), max. sink current 1 mA	TPS74401 data sheet
EN_GT_L	J2-79	GT_DCDC	NC7S08P5X data sheet	PG_GT_L	J2-97	External pull-up needed (max. 5.5V), max. sink current 1 mA	TPS74801 data sheet
EN_PLL_PWR	J2-77	6V	TPS82085SIL data sheet	PG_PLL_1V8	J2-80	External pull-up needed (max. 5.5V), max. sink current 1 mA	TPS82085SIL data sheet

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Power Rail Name	B2B J1 Pins	B2B J2 Pins	B2B J3 Pins	Directions	Note
PL_DCIN	151, 153, 155, 157, 159	-	-	Input	-
DCDCIN	-	154, 156, 158, 160, 153, 155, 157, 159	-	Input	-
LP_DCDC	-	138, 140, 142, 144	-	Input	-
PS_BATT	-	125	-	Input	-
GT_DCDC	-	-	157, 158, 159, 160	Input	-
PLL_3V3	-	-	152	Input	U5 (programmable PLL) 3.3V nominal input
SI_PLL_1V8	-	-	151	Output	Internal voltage level 1.8V nominal output
PS_1V8	-	99	147, 148	Output	Internal voltage level 1.8V nominal output
PL_1V8	91, 121	-	-	Output	Internal voltage level 1.8V nominal output
DDR_1V2	-	135	-	Output	Internal voltage level 1.2V nominal output

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Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	-0.3	74	V	TPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG
DCDCIN	-0.3	74	V	TPS82085SIL / TPS51206 data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC	-0.3	4	V	TPS3106K33DBVR data sheet
GT_DCDC	-0.3	74	V	TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
PS_BATT	-0.5	2	V	Xilinx DS925 data sheet
PLL_3V3	-0.5	3.8	V	Si5345/44/42 data sheet
VCCO for HD I/O banks	-0.5	3.4	V	Xilinx DS925 data sheet
VCCO for HP I/O banks	-0.5	2	V	Xilinx DS925 data sheet
VREF	-0.5	2	V	Xilinx DS925 data sheet
I/O input voltage for HD I/O banks	-0.55	VCCO + 0.55	V	Xilinx DS925 data sheet
I/O input voltage for HP I/O banks	-0.55	VCCO + 0.55	V	Xilinx DS925 data sheet
PS I/O input voltage (MIO pins)	-0.5	VCCO_PSIO + 0.55	V	Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally
Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage	-0.5	1.2	V	Xilinx DS925 data sheet
Voltage on input pins of NC7S08P5X 2-Input AND Gate	-0.5	VCC + 0.5	V	NC7S08P5X data sheet, see schematic for VCC
Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41	-0.3	VDD + 0.3	V	TPS3106 data sheet, VDD = LP_DCDC
"Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD)	-0.3	7	V	TPS82085SIL data sheet
Storage temperature (ambient)	-40	100	°C	ROHM Semiconductor SML-P11 Series data sheet

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Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	23.53	3.6	V	EN63A0QI / TPS82085SIL data sheet *Note: PG_PL will be pullup with this voltage/ Limit is LP_DCDC over EN/PG
DCDCIN	3.13	3.6	V	TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC	23.53	3.6	V	TPS82085SIL / TPS3106 TPS3106K33DBVR data sheet
GT_DCDC	23.53	3.6	V	TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT	1.2	1.5	V	Xilinx DS925 data sheet
PLL_3V3	3.14	3.47	V	Si5345/44/42 data sheet 3.3V typical
VCCO for HD I/O banks	1.14	3.4	V	Xilinx DS925 data sheet
VCCO for HP I/O banks	0.95	1.9	V	Xilinx DS925 data sheet
I/O input voltage for HD I/O banks.	-0.2	VCCO + 0.2	V	Xilinx DS925 data sheet
I/O input voltage for HP I/O banks	-0.2	VCCO + 0.2	V	Xilinx DS925 data sheet
PS I/O input voltage (MIO pins)	-0.2	VCCO_PSIO + 0.2	V	Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally
Voltage on input pins of NC7S08P5X 2-Input AND Gate	0	VCC	V	NC7S08P5X data sheet, see schematic for VCC
Voltage on input pin 'MR' of TPS3106K33DBVR Voltage Monitor, U41	0	VDD	V	TPS3106 data sheet, VDD = LP_DCDC

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Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm5mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

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Document Change History

modified- correction in PLL_RST

correction MGT Lane assignment

v. Nov 2018 Aug 2018 Jun 2018 Nov 2017

Date

Revision

Contributors

Description

Page info

modified-date

infoType	Modified

date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

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infoType	Modified by
dateFormat	yyyy-MM-dd
type	Flat

typo

DDR section

2022-09-13

v.41

Vadim Yunitski

Updated PG_PL pull-up resistor requirements

2021-09-07

V.39

John Hartfiel

Correction Power section

2021-05-17

v.37

John Hartfiel

typo correction in DDR section

2021-03-11

v.35

Antti Lukats

typo correction in PLL_RST
add pin on power rails table
correction MGT Lane assignment
correction MGT CLK assignment

2019-01-27

v.

07 Jan 2019

30

Martin Rohrmüller

Corrected clock connection to J2

2018-11-20

v.29

John Hartfiel

Notes for power supply

2018-08-27

v.27

John Hartfiel

typo correction SI5345 I2C address

2028-06-28

v.26

John Hartfiel

typo SI5348 B2B IOs + link correction

2017-11-13

v.24

Ali Naseri

updated B2B connector max. current rating per pin

2017-11-13

v.22

John Hartfiel

rework B2B section

2017-10-20

v.21

Ali Naseri

Update links (pdf, documentation) to revision 4
ES silicon note removed

2017-08-28

v.15

John Hartfiel

Update section: Variants Currently In Production

2017-08-28

v.14

Jan Kumann

Block diagram changed.
SPI flash section fixed.
Few smaller improvements.

2017-08-15

v.12

Vitali Tsiukala

Changed signals count in the B2B connectors table

2017-08-15

v.11

John Hartfiel, Ali Naseri

PCB REV04 Initial release
update boot mode section

2017-02-06

v.1

Jan Kumann

Initial document

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Programmable PLL Clock Generator

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