Versions Compared

Old Version 36

changes.mady.by.user John Hartfiel

Saved on

compared with

New Version Current

changes.mady.by.user John Hartfiel

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

Programmable PLL Clock Generator

...

Enable-SignalB2B Connector PinMax. VoltageNote
Power-Good-SignalB2B Connector PinPull-up ResistorNote
EN_LPDJ2-1086VTPS82085SIL data sheet
LP_GOODJ2-1064K7, pulled up to LP_DCDC-
EN_FPDJ2-102DCDCINNC7S08P5X data sheet
PG_FPDJ2-1104K7, pulled up to DCDCIN-
EN_PLJ2-101PL_DCINleft floating for logic high
(drive to GND for logic low)
PG_PLJ2-104External pull-up needed (max. voltage GT_DCDC),
max. sink current 		1 mA4K7, pulled up to PL_DCIN

TPS82085SIL /
NC7S08P5X data sheet

EN_DDRJ2-112DCDCINNC7S08P5X data sheet
PG_DDRJ2-1144K7, pulled up to DCDCIN-
EN_PSGTJ2-84DCDCINNC7S08P5X data sheet
PG_PSGTJ2-82External pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74801 data sheet
EN_GT_RJ2-95GT_DCDCNC7S08P5X data sheet
PG_GT_RJ2-91External pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74401 data sheet
EN_GT_LJ2-79GT_DCDCNC7S08P5X data sheet
PG_GT_LJ2-97External pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS74801 data sheet
EN_PLL_PWRJ2-776VTPS82085SIL data sheet
PG_PLL_1V8J2-80External pull-up needed (max. 5.5V),
max. sink current 1 mA		TPS82085SIL data sheet

...

Parameter

MinMax

Unit

Notes / Reference Document

PL_DCIN-0.374VTPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG
DCDCIN-0.374VTPS82085SIL / TPS51206 data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.374VTPS82085SIL data sheet / Limit is LP_DCDC over EN/PG
PS_BATT-0.52VXilinx DS925 data sheet
PLL_3V3-0.53.8VSi5345/44/42 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
VREF-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally

Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx DS925 data sheet

Voltage on input pins of
NC7S08P5X 2-Input AND Gate

-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

-0.3VDD + 0.3V

TPS3106 data sheet,
VDD = LP_DCDC

"Enable"-signals on TPS82085SIL
(EN_PLL_PWR, EN_LPD)		-0.37VTPS82085SIL data sheet

Storage temperature (ambient)

-40

100

°C

ROHM Semiconductor SML-P11 Series data sheet

...

ParameterMinMaxUnitNotes / Reference Document
PL_DCIN23.533.6V

EN63A0QI / TPS82085SIL data sheet

*Note: PG_PL will be pullup with this voltage

/ Limit is LP_DCDC over EN/PG

DCDCIN3.133.6VTPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG
LP_DCDC23.533.6VTPS82085SIL / TPS3106 TPS3106K33DBVR data sheet
GT_DCDC23.533.6VTPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT1.21.5VXilinx DS925 data sheet
PLL_3V33.143.47VSi5345/44/42 data sheet
3.3V typical
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Voltage on input pins of
NC7S08P5X 2-Input AND Gate		0VCCV

NC7S08P5X data sheet,
see schematic for VCC

Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41

0VDDV

TPS3106 data sheet,
VDD = LP_DCDC

...

Document Change History

modified- correction in PLL_RST
  • add pin on power rails table
  • correction MGT Lane assignment
    • correction MGT CLK assignment
     Date

    Revision

    		ContributorsDescription

    Page info

    		modified-date

    infoTypeModified

    date
    dateFormatyyyy-MM-dd
    typeFlat

    Page info
    infoTypeCurrent version
    dateFormatyyyy-MM-dd
    prefixv.
    typeFlat

    Page info
    infoTypeModified by
    dateFormatyyyy-MM-dd
    typeFlat

    • typo DDR section

    2022-09-13

    v.41

    Vadim Yunitski 

    • Updated PG_PL pull-up resistor requirements
    2021-09-07V.39John Hartfiel
    • Correction Power section
    2021-05-17v.37John Hartfiel
    • typo correction in DDR section
    2021-03-11v.35Antti Lukats
    • typo correction in PLL_RST
    • add pin on power rails table
    • correction MGT Lane assignment
    • correction MGT CLK assignment

    2019-01-27

    		v.30Martin Rohrmüller
    • Corrected clock connection to J2

    2018-11-20

    v.29

    		John Hartfiel
    • Notes for power supply

    2018-08-27

    		v.27John Hartfiel
    • typo correction SI5345 I2C address

    2028-06-28

    		v.26John Hartfiel
    • typo SI5348 B2B IOs + link correction

    2017-11-13

    		v.24Ali Naseri
    • updated B2B connector max. current rating per pin

    2017-11-13


    v.22


    		John Hartfiel
    • rework B2B section
    2017-10-20

    v.21

    		Ali Naseri
    • Update links (pdf, documentation) to revision 4
    • ES silicon note removed
    2017-08-28
    v.15
    		John Hartfiel

    • Update section: Variants Currently In Production

    2017-08-28v.14Jan Kumann
    • Block diagram changed.
    • SPI flash section fixed.
    • Few smaller improvements.
    2017-08-15v.12Vitali TsiukalaChanged signals count in the B2B connectors table
    2017-08-15

    v.11

    		John Hartfiel, Ali Naseri
    • PCB REV04 Initial release
    • update boot mode section
    2017-02-06v.1Jan KumannInitial document

    Disclaimer

    Include Page
    IN:Legal Notices
    IN:Legal Notices