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The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale KU035 FPGA, 2 banks of 512 MByte DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor SoMs are mechanically compatible.
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- Xilinx Kintex UltraScale FPGA, U1
- Ultra Performance Oscillator @25.000000 MHz, U3
- 12A PowerSoC DC-DC Converter (0.95V), U14
- 12A PowerSoC DC-DC Converter (0.95V), U7
- Low-jitter Precision LVDS Oscillator @200.0000 MHz, U11
- Low-Dropout dropout (LDO) Linear Regulator linear regulator (MGTAVTT 1.20V), U8
- Low-Dropout dropout (LDO) Linear Regulator linear regulator (MGTAVCC 1.02V), U12
- Samtec Razor Beam™ LSHM-150 B2B connector, JM1
- Samtec Razor Beam™ LSHM-150 B2B connector, JM2
- Samtec Razor Beam™ LSHM-130 B2B connector, JM3
- Programmable Quad Clock Generatorquad clock generator, U2
- 32 MByte SPI QSPI Flash, U6
- 4 Gbit DDR4 SDRAM, U4
- 4 Gbit DDR4 SDRAM, U5
- System Controller CPLD, U18
- Low-Dropout dropout (LDO) Linear Regulator linear regulator (MGTAUX), U9Ultralow-
- Power Low-Dropout Ultra-low power low-dropout (LDO) Regulator regulator (VBATT), U19
Key Features
- Xilinx Kintex UltraScale KU35 XCKU035 FPGA
- Rugged for industrial applicationapplications
- 2 banks of 512 MByte, 16 bit wide DDR4 SDRAM
- 256 Mbit (32 MByte) SPI QSPI Flash
- Size: 40 x 50 mm
- 3 mm mounting holes for skyline heat spreader
- B2B Connectors: 3 x Samtec Razor Beam LSHM, 260 terminals total
- User I/O: HR 12, HP 132
- Serial transceiver: GTH 8 lanes (TX/RX)
- GT clock inputs: 2 - Clocking
- Si5338 - 4 output PLLs, GT and PL clocks
- 200 MHz LVDS oscillator - All power supplies on-board, single power source operation
- Evenly spread supply pins for optimized signal integrity
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Storage device name | Content | Notes | ||||||
|---|---|---|---|---|---|---|---|---|
OTP Flash area | ... | Empty |
Signals, Interfaces and Pins
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For detailed information about the pin out, please refer to the Pin-out Tables.
I2C Interface
On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:
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There are two PL bank 65 IO pins (PLL_SCL and PLL_SDA) reserved as I2C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I2C bus slave address is 0x70.
Additionally, two PL bank 65 IO pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I2C connectivity, otherwise these pins are ordinary IOs
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JTAG Interface
JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.
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| Note |
|---|
| JTAGMODE pin 89 in B2B connector JM1 should be kept low or grounded for normal operation. |
System Controller CPLD I/O Pins
Special purpose pins are connected to smaller the System Controller CPLD and have following default configuration:
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| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Green | System Controlled Controller CPLD, bank 3 | Exact function is defined by SC CPLD firmware. |
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Processing System (PS) Peripherals
| Name | IC | ID | PS7 | MIO | Notes |
|---|---|---|---|---|---|
| QSPI Flash | N25Q256A | U6 | |||
| PLL quad clock generator | SI5338A | U2 |
Clocking
| Clock Signal | Frequency | ICSource | FPGA | Notes |
|---|---|---|---|---|
PLL - Phase-Locked Loop
There is a Si5338 programmable quad clock generator chip on-board.
PLL outputs
| - | 25.000000 MHz | SiT8208 (U3), CLK | - | Reference clock input for Si5338 PLL quad clock generator. |
| CLK200M | 200.0000 MHz | DSC1123 (U11), OUT | R25/R26, bank 45 | |
| CLK0 | User programmable | Si5338 (U2), CLK3 | T24/T25, bank 45 | |
| CLK1 | User programmable | Si5338 (U2), CLK0 | R23/P23, bank 45 | |
| MGT_CLK0 | Baseboard supplied | JM3-31, JM3-33 | Y5/Y6, bank 225 | Bank 225 MGTs clock source from baseboard. |
| MGT_CLK1 | User programmable | Si5338 (U2), CLK1 | V5/V6, bank 225 | Bank 225 MGTs clock source from on-board PLL quad clock generator. |
| MGT_CLK2 | Baseboard supplied | JM3-32, JM3-34 | AD6/AD5, bank 224 | Bank 224 MGTs clock source from baseboard. |
| MGT_CLK3 | User programmable | Si5338 (U2), CLK2 | AB6/AB5, bank 224 | Bank 224 MGTs clock source from on-board PLL quad clock generator |
| I/O | Default Frequency | Notes | ||
|---|---|---|---|---|
| CLK0 | Connected to FPGA pins P23/R23 as CLK1. | |||
| CLK1 | Connected to MGT_CLK1. | |||
| CLK2 | Connected to MGT_CLK3. | |||
| CLK3 | Connected to FPGA pins T24/T25 as CLK0. |
Power and Power-On Sequence
Power Supply
Power Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.
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Variants Currently In Production
| Module Variant | FPGA Chip | MGT/PL Clock [MHz] |
|---|---|---|
| TE0841-01-035-1C | XCKU035-1SFVA784C | |
TE0841-01-035-1I | XCKU035-1SFVA784I | |
TE0841-01-035-2I | XCKU035-2SFVA784I |
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Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
VIN supply voltage | V | - | ||
Storage temperature | -40 | +85 | °C | - |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage |
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
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Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Weight
25 47 g - Plain module.
9 g - Set of bolts and nuts.
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