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Overview

Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0808" for downloadable version of this manual and the rest of available documentation.

The Trenz Electronic TE0808 is an industrial-grade MPSoC UltraSoM integrating a Xilinx Zynq UltraScale+, 4 x 4 Gbit (256 MByte) max. 8 GByte DDR4 SDRAM with 1664-bit Bit width databus width, 2 x 256 MBit (32 MByte) connection, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

Block Diagram

Figure 1: TE0808-03 Block Diagram

Main Components

Figure 2: TE0808-03 MPSoC module

1. Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
2. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
3. Red LED (DONE), D1
4. 256Mx16 DDR4-2400 SDRAM, U12
5. 256Mx16 DDR4-2400 SDRAM, U9
6. 256Mx16 DDR4-2400 SDRAM, U2
7. 256Mx16 DDR4-2400 SDRAM, U3
8. 12A PowerSoC DC-DC DCDC converter, U4
9. Quartz crystal, Y1
10. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
11. 10-channel programmable clock generator, U5
12. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
13. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Quartz crystal, Y2
17. 256 Mbit serial NOR Flash memory, U7
18. 256 Mbit serial NOR Flash memory, U17

Key Features

• MPSoC: ZYNQ UltraScale+ ZU9EG 900 pin package
• Memory
  - 64-Bit DDR4, 8 GByte maximum
  - Dual SPI boot Flash in parallel, 512 MByte maximum
• User I/O
  - 65 x MIO, 48 x HD (all),  156 x HP (3 banks)
  - Serial transceiver: 4 x GTR + 16 x GTH
  - Transceiver clocks inputs and outputs
  - PLL clock generator inputs and outputs
• Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
• B2B connectors: 4 x 160 pin
• Si5345 - 10 output PLL
• All power supplies on board, single 3.3V power source required
  - 14 on-board DCDC regulators and 13 LDOs
  - LP, FP, PL separately controlled power domains
• Support for all boot modes (except NAND) and scenarios
• Support for any combination of PS connected peripherals

Initial Delivery State

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

Board to Board (B2B) connectors

The TE0808 MPSoC UltraSoM has four Board to Board (B2B) connectors with 160 contacts per connector.

Each connector has a specific arrangement of the signal-pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq Ultrascale+ MPSoC like I/O-banks, interfaces and Gigabit transceivers
or to the on-board peripheral ICs of the UltraSoM.

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Bank 230 (GTH)

4 GTH lanes

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B230_RX3_P, B230_RX3_N, pins J1-3, J1-5
B230_TX3_P, B230_TX3_N, pins J1-2, J1-4

B230_RX2_P, B230_RX2_N, pins J1-9, J1-11
B230_TX2_P, B230_TX2_N, pins J1-8, J1-10

B230_RX1_P, B230_RX1_N, pins J1-15, J1-17
B230_TX1_P, B230_TX1_N, pins J1-14, J1-16

B230_RX0_P, B230_RX0_N, pins J1-21, J1-23
B230_TX0_P, B230_TX0_N, pins J1-20, J1-22

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GTH lane

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Bank 229 (GTH)

4 GTH lanes

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B229_RX3_P, B229_RX3_N, pins J1-27, J1-29
B229_TX3_P, B229_TX3_N, pins J1-26, J1-28

B229_RX2_P, B229_RX2_N, pins J1-33, J1-35
B229_TX2_P, B229_TX2_N, pins J1-32, J1-34

B229_RX1_P, B229_RX1_N, pins J1-39, J1-41
B229_TX1_P, B229_TX1_N, pins J1-38, J1-40

B229_RX0_P, B229_RX0_N, pins J1-45, J1-47
B229_TX0_P, B229_TX0_N, pins J1-44, J1-46

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GTH lane

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Bank 228 (GTH)

4 GTH lanes

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B228_RX3_P, B228_RX3_N, pins J1-27, J1-29
B228_TX3_P, B228_TX3_N, J1-26, J1-28

B228_RX2_P, B228_RX2_N, pins J1-33, J1-35
B228_TX2_P, B228_TX2_N, J1-32, J1-34

B228_RX1_P, B228_RX1_N, pins J1-39, J1-41
B228_TX1_P, B228_TX1_N, J1-38, J1-40

B228_RX0_P, B228_RX0_N, pins J1-45, J1-47
B228_TX0_P, B228_TX0_N, J1-44, J1-46

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Bank 66 (HP)
LVDS pairs 1 ... 24

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VCCO66
pins J1-90, J1-120

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VCCO66

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Schematic names / Connector pins

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CLK0_P, CLK0_N, pins J2-3, J2-1
CLK7_P, CLK7_N, pins J2-7, J2-9
CLK8_P, CLK8_N, pins J2-13, J2-15

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output from Si5351A-B-GM
programmable PLL clock generator

LVDS-pairs

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IN1_P, IN1_N, pins J2-3, J2-1

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input to Si5351A-B-GM
programmable PLL clock generator

LVDS-pair

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reference clock input to MPSoC's bank

LVDS-pairs

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reference clock input to MPSoC's bank

LVDS-pair

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Bank 128 (GTH)

4 GTH lanes

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B128_RX3_N, B128_RX3_P, pins J2-28, J2-30
B128_TX3_N, B128_TX3_P, pins J2-25, J2-27

B128_RX2_N, B128_RX2_P, pins J2-34, J2-36
B128_TX2_N, B128_TX2_P, pins J2-31, J2-33

B128_RX1_N, B128_RX1_P, pins J2-40, J2-42
B128_TX1_N, B128_TX1_P, pins J2-37, J2-39

B128_RX0_N, B128_RX0_P, pins J2-46, J2-48
B128_TX0_N, B128_TX0_P, pins J2-43, J2-45

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GTH-lanes, each composed of two LVDS-pairs

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Bank 505 (GTR)

4 GTR lanes

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B505_RX3_N, B505_RX3_P, pins J2-52, J2-54
B505_TX3_N, B505_TX3_P, pins J2-49, J2-51

B505_RX2_N, B505_RX2_P, pins J2-58, J2-60
B505_TX2_N, B505_TX2_P, pins J2-55, J2-57

B505_RX1_N, B505_RX1_P, pins J2-64, J2-66
B505_TX1_N, B505_TX1_P, pins J2-61, J2-63

B505_RX0_N, B505_RX0_P, pins J2-70, J2-72
B505_TX0_N, B505_TX0_P, pins J2-67, J2-69

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DONE, pin J2-116 (indicated by red LED D1)
PROG_B, pin J2-100
INIT_B, pin J2-98
SRST_B, pin J2-96
MODE0, pins J2-109
MODE1, pins J2-107
MODE2, pins J2-105
MODE3, pins J2-103
ERR_OUT, pin J2-88
ERR_STATUS, pin J2-86
PUDC_B, pin J2-127

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PS_1.8V
(PUDC_B pulled-up to PL_1V8)

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TCK, pin J2-120
TDI, pin J2-122
TDO, pin J2-124
TMS, pin J2-126

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DX_P, DX_N, pins J2-119, J2-121

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PLL_FINC, pin J2-81
PLL_LOLN, pin J2-85
PLL_SEL0, pin J2-93
PLL_SEL1, pin J2-87
PLL_FDEC, pin J2-94
PLL_RST, pin J2-59
PLL_SCL, pin J2-90 (I²C interface)
PLL_SDA, pin J2-92 (I²C interface)

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Control interface to Si5351A-B-GM
programmable PLL clock generator

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EN_PSGT, pin J2-84
PG_PSGT, pin J2-82

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"Enable"- and corresponding
"Power Good"-Signal

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U29 (DCDC)
U15 (DCDC)

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EN_LPD, pin J2-108
LP_GOOD, pin J2-106

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"Enable"- and corresponding
"Power Good"-Signal

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U40 (DCDC)
U31 (DCDC)

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EN_DDR, pin J2-112
PG_DDR, pin J2-114

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"Enable"- and corresponding
"Power Good"-Signal

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EN_PLL_PWR, pin J2-77
PG_PLL_1V8, pin J2-80

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"Enable"- and corresponding
"Power Good"-Signal

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EN_GT_L, pin J2-79
PG_GT_L, pin J2-97

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"Enable"- and corresponding
"Power Good"-Signal

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EN_GT_R, pin J2-95
PG_GT_R, pin J2-91

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"Enable"- and corresponding
"Power Good"-Signal

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EN_PL, pin J2-101
PG_PL, pin J2-104

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EN_PL connected to 'PL_DCIN'
PG_PL: extern pull-up needed, max. 'GT_DCDC'

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"Enable"- and corresponding
"Power Good"-Signal

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Leave unconnected or connect
to VDD (LP_DCDC) when unused.

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Bank 48 (HD)
LVDS pairs 1 ... 12

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B48_L1_P ... B48_L12_P
B48_L1_N ... B48_L12_N

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VCCO48
pins J3-15, J3-16

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VCCO max. 3.3V
usable as single-ended I/O's

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Bank 47 (HD)
LVDS pairs 1 ... 12

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B47_L1_P ... B47_L12_P
B47_L1_N ... B47_L12_N

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VCCO47
pins J3-43, J3-44

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VCCO max. 3.3V
usable as single-ended I/O's

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input to Si5351A-B-GM
programmable PLL clock generator

LVDS-pair

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B228_CLK0_P, B228_CLK0_N, pins J3-10, J3-12

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reference clock input to MPSoC's bank

LVDS-pairs

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reference clock input to MPSoC's bank

LVDS-pairs

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reference clock input to MPSoC's bank

LVDS-pairs

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GT_DCDC, pins J3-157, J3-158, J3-159, J3-160

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PS_1V8, pins J3-147, J3-148

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Bank 64 (HP)
LVDS pairs 1 ... 24

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B64_L1_P ... B64_L24_P
B64_L1_N ... B64_L24_N

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VCCO64
pins J4-58, J4-106

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VCCO max. 1.8V
usable as single-ended I/O's

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Bank 65 (HP)
LVDS pairs 1 ... 24

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B65_L1_P ... B65_L24_P
B65_L1_N ... B65_L24_N

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VCCO65
pins J4-69, J4-105

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VCCO max. 1.8V
usable as single-ended I/O's

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B_64_T0 ... B_64_T3
pins J4-8, J4-6, J4-4, J4-2

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VCCO64
pins J4-58, J4-106

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VCCO max. 1.8V

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B_65_T0 ... B_65_T3
pins J4-7, J4-5, J4-3, J4-1

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VCCO65
pins J4-69, J4-105

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VCCO max. 1.8V

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Reference Input Voltage

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Table 2: B2B Connector pin assignment of the TE0808-03 UltraSoM

For detailed information about the B2B pin-out, please refer to the Pin-out table.

Quad-SPI Flash memory

The TE0808-03 UltraSoM is equipped with two Micron Serial NOR Flash Memory with 256 Mbit (32 Mbyte) storage capacity each. The flash memory ICs with the schematic designators U7 and U17 are connected to bank 500 (PSMIO) of the Zynq MPSoC module via QSPI interface.

Following table shows the mapping of the MIO-pins to the flash memory ICs.

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Chip-select,

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Chip-select,
low-active, pulled-up to PS_1V8

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SoM.

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS-pairs or single ended I/O's to the B2B connectors.

Table 2: B2B connector pin-outs of available PL and PS banks of the TE0808-03 SoM

For detailed information about the B2B pin-out, please refer to the Pin-out table.

MGT lanes

The B2B connector J1 and J2 provide also access to the MGT-banks of the Zynq Ultrascale+ MPSoC. There are 20 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).

The MGT-banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT-lanes are available on the B2B connectors:

Table 3: B2B connector pin-outs of available MGT-lanes of the MPSoC

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage 'PS_1V8'.

Table 4: B2B connector pin-out of JTAG interface

Configuration bank control signals

The Xilinx Zynq Ultrascale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B-connector J2.

Table 5: B2B connector pin-out of MPSoC's PS configuration bank

Analog Input

The Xilinx Zynq Ultrascale+ MPSoC provides input-pins for differential analog values. The pins are exposed to B2B-connector J2.

Table 6: B2B connector pin-out of analog input pins

Quad-SPI Flash memory

The TE0808-03 SoM is equipped with two Serial Flash Memory with up to 512 Mbyte storage capacity each. The flash memory ICs with the schematic designators U7 and U17 are connected to bank 500 (PSMIO) of the Zynq MPSoC module via QSPI interface, enabling a 8-Bit width databus connection.

Following table shows the mapping of the MIO-pins to the flash memory ICs.

Table 7: Flash memory QSPI-interface

DDR4 SDRAM

The TE0808-03 UltraSoM is equipped with with four DDR4-2400 SDRAM modules with up to 8 Gbyte memory density. The SDRAM modules are connected to the Zynq MPSoC's PS DDR-controller (bank 504) with a 64-bit databus width.

LEDs

TE0808 has one red LED (D1) which reflects MPSoC's 'DONE' signal. This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly.

Clocking

Programmable Clock Generator

Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

Table 8: Programmable PLL clock generator input/output

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

Table 9: B2B connector pin-out of Si5345A programmable clock generator

The TE0808-03 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock-signals.

Table 10: Reference clock-signals to PS configuration bank 503

Power and Power-On Sequence

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0808-03 module with the Xilinx Zynq Ultrascale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq Ultrascale+ MPSoC has multiple power domains, whereby each power domain requires its particular extern DCDC converters.

The Processing System contains three Power Domains:

• Battery Power Domain (BBRAM and RTC)
• Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
• Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0808-03 SoM, following Power Domains can be powered up individually with power rails available on the B2B connectors:

• Full-Power Domain, supplied by power rail 'DCDCIN'
• Low-Power Domain, supplied by power rail 'LP_DCDC'
• Programmable Logic, supplied by power rail 'PL_DCIN'
• Battery Power Domain, supplied by power rail 'PS_BATT'

Each Power Domain has its own "Enabling"- and "Power Good"-signal. The power rail 'GT_DCDC' is necessary for generating the supply voltages for the high speed Gigabit Transceivers units of the Zynq Ultrascale+ MPSoC.

Power-On Sequence utilizing DCDC control signals

To power up the TE0808-03 SoM properly, a specific sequence must be kept of enabling the on-board DCDC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The first activated Power Domain is the Low-Power Domain. Therefore, the power rail 'LP_DCDC' have to be powered up and the Enable-signal 'EN_LPD' (pin J2-108, 7V max.) have to be asserted. The resulting Power-Good-Signal 'LP_GOOD' (pin J2-106) will go high after the voltages of the Low-Power Domain are properly powered up.

Image Added

Figure 3: Low-Power Domain

The second activated Power Domain is the Programmable Logic. Therefore, the power rail 'PL_DCIN' have to be powered up and the Enable-signal 'EN_PL' (pin J2-101) have to be asserted by pulling this pin up to the voltage 'LP_DCDC' or left floating (drive to GND for disabling). The resulting Power-Good-Signal 'PG_PL' (pin J2-104) will go high after the voltages of the Programmable Logic Domain are properly powered up. The signal 'PG_PL' needs an extern pull-up (max. voltage 'GT_DCDC').

Image Added

Figure 4: Programmable Logic Domain

Also as second activated Power Domain is the Full-Power Domain. Therefore, the power rail 'DCDCIN' have to be powered up and the Enable-signals 'EN_FPD' (pin J2-102) and 'EN_DDR' (J2-112) have to be asserted (max. voltage 'DCDCIN'). The resulting Power-Good-Signals 'PG_FPD' (pin J2-110) and 'PG_DDR' (J2-114) will go high after the voltages of the Programmable Logic Domain are properly powered up. In the following, the PSGT voltages (see figure 3) can be powered up by asserting the Enable-signal 'EN_PSGT' (pin J2-84, max. voltage 'DCDCIN'). The resulting Power-Good-Signal 'PG_PSGT' (pin J2-82) needs an extern pull-up (max. 6V).

Image Added

Figure 5: Full-Power Domain

The supply voltages for the MGT units of the MPSoC will be powered up last. Therefore, the power rail 'GT_DCDC' have to be powered up and the Enable-signals 'EN_GT_R' (pin J2-95), 'EN_GT_L' (pin J2-79) and 'EN_PLL_PWR' (J2-77, 7V max.) have to be asserted (max. voltage 'GT_DCDC'). The resulting Power-Good-Signals 'PG_GT_R' (pin J2-91), 'PG_GT_L' (pin J2-97) and 'PG_PLL_1V8' (J2-80) will go high after the voltages of the Programmable Logic Domain are properly powered up. The three Power-Good-Signals need an extern pull-up (max. 6V).

Image Added

Figure 6: Powering up MGT supply voltages

The voltages 'LP_DCDC' and 'LP_0V85' are monitored by a the voltage monitor circuit U41, which generates the POR_B signal at Power-On. A manual reset is also possible the driving the MR-pin (J2-83) to GND. Leave unconnected or connect to VDD (LP_DCDC) when unused.

Image Added

Figure 7: Voltage monitor circuit

Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are 3-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808-03 SoM.

Power Rails

Table 15: Power rails of the MPSoC module on accessible connectors

Bank Voltages

Table 16: Range of MPSoC module's bank voltages

Table 3: Flash memory QSPI-interface

DDR4-2400 SDRAM

The TE0808-03 UltraSoM is equipped with with four Nanya NT5AD256M16B2-GN DDR4-2400 SDRAM modules with 4 Gbit (256 MByte) memory density. The SDRAM modules are connected to the PS DDR controller (bank 504) with 16 bit databus width respectively.

LEDs

TE0808 has one red LED (D1) which reflects MPSoC's 'DONE' signal. This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly.

Clocking

Programmable Clock Generator

Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

...

Power and Power-On Sequence

The TE0808-03 module with the Xilinx Zynq Ultrascale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management is achieved by establishing Power Domains for power isolation. The Zynq Ultrascale+ MPSoC is composed of multiple power domains, whereby each power domain requires their particular extern DCDC converters.

The Processing System contains three Power Domains:

• Battery Power Domain, needed for BBRAM and RTC
• Full-Power Domain, needed for Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity
• Low-Power Domain, needed for Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

The following diagram shows the sequence of enabling the on-board DCDC converters dedicated to the particular Power Domains and powering up the needed voltages.

On the TE0808-03 SoM, following Power Domains can be powered up individually with power rails available on the B2B connectors:

• Full-Power Domain, supplied by power rail 'DCDCIN'
• Low-Power Domain, supplied by power rail 'LP_DCDC'
• Programmable Logic, supplied by power rail 'PL_DCIN'
• Battery Power Domain, supplied by power rail 'PS_BATT'

Each Power Domain has its own "Enabling"- and "Power Good"-signal. The power rail 'GT_DCDC' generates the supply voltages for the high speed Gigabit Transceivers units of the Zynq Ultrascale+ MPSoC.

For the absolute maximum ratings and the recommended operating conditions of the power rails, see section 'Technical Specifications'.

Image Removed

Figure 3: TE0808-03 Power-On sequence diagram

B2B connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

• Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 4mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

...

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

17 g - Plain module

Revision History

Hardware Revision History

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Document Change History

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