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Table of Contents

Table of Contents

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On https://wiki.trenz-electronic.de/display/PD/TE0782-02+TRM the online version of this manual and other documents can be found.
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The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC. It is equipped with a Xilinx Zynq-7 (XC7Z035, XC7Z045 or XC7Z100).

...

All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options and for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

Block Diagram

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Main Components

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The SoM TE0782-02 This SoM has following peripherals components on board:

  • 2 x Gbps Ethernet PHY transceiver
  • 32-Bit DDR3 SDRAM 1Gbyte
  • 32 MByte QSPI Flash Memory
  • eMMC (4 GByte in standard configuration)
  • 2 x USB PHY transceiver
  • 16 GTX high-performance transceiver
  • powerful switch-mode power supplies for all on-board voltages
  • large number of configurable I/Os is provided via rugged high-speed stacking strips

Block Diagram

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Key Features

  • Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoM
  • Rugged for shock and high vibration
  • Dual ARM Cortex-A9 MPCore
    • 1 GByte RAM (32-Bit wide DDR3)
    • 32 MByte QSPI Flash memory
    • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
    • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
    • 4 GByte eMMC (optional up to 64GByte)
  • 2 x MAC-Address EEPROMs
  • optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM) or optional 2 x 64 MByte HyperFLASH
  • Temperature compensated RTC (real-time clock)
  • Si5338 PLL for GTX Transceiver clocks
  • Plug-on module with 3 x 160-pin high-speed strips
    • 16 GTX high-performance transceiver
    • GT transceiver clock inputs
    • 254 FPGA I/O's (125 LVDS pairs)
  • On-board high-efficiency DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
  • User LED

Assembly options for cost or performance optimization available upon request.

Signals, Interfaces and Pins

System Controller CPLD I/O Pins

Special purpose pins to configure and operate the System Controller CPLD (IC U14) used by TE0782

NameNote
BOOTMODEuser configurable (CPLD)
CONFIGXuser configurable (CPLD)
JTAGENBspecial mode pin for SC CPLD
RESINSystem-reset
CLPD_GPIO0Function defined by CPLD Firmware
CLPD_GPIO1Function defined by CPLD Firmware
CLPD_GPIO2Function defined by CPLD Firmware
CLPD_GPIO3Function defined by CPLD Firmware
CLPD_GPIO4Function defined by CPLD Firmware
CLPD_GPIO5Function defined by CPLD Firmware
CLPD_GPIO6 
CLPD_GPIO7 

Small CPLD controls some functions of the SoM, this CPLD can be updated by the end user if support is designed in on customer base.

Boot Modes

TE0782 supports primary boot from

  • SPI Flash

Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).

JTAG

JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

SignalB2B Pin
TCKJ3:  141
TDIJ3:  147
TDOJ3:  148
TMSJ3:  1142

 

CPLD-JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

SignalB2B Pin
M_TCKJ3:  81
M_TDIJ3:  87
M_TDOJ3:  82
M_TMSJ3:  88
Note

JTAGENB pin in J3 should be kept low or grounded for normal operation.

Clocking

Silabs Multisynth PLL Si5338 can deliver GT reference clocks to all 4 GT Banks. Additionally a GT Reference clock can be generated on the base board for any of the 4 GT Banks. There is reference clock available on the TE0782 for Si5338, optionally external reference clock can be supplied from the base.

ClockFrequencyICZYNQ PS / PLNotes
PS CLK33.3333 MHzU61PS CLKPS Subsystem main clock
10/100/1000 Mbps ETH PHYs reference25 MHzU11- 
USB PHY reference52 MHzU7- 

PLL reference

25 MHz

U3

-

 

GT REFCLK1

-

B2B connector

BANK110, Pin AC7/AC8

Externally supplied from base

GT REFCLK4

-

B2B connector

BANK111, Pin U7/U8

Externally supplied from base

Si5338 CLK0 U2BANK110, Pin AA8/AA7?
Si5338 CLK1 U2BANK109, Pin AF10/AF9?
Si5338 CLK2 U2BANK111, Pin W8/W7?
Si5338 CLK3 U2BANK112, Pin N8/N7?

Processing System (PS) Peripherals

  1. Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoC
  2. Lattice Semiconductor MachXO2 1200HC System Controller CPLD
  3. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width)
  4. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width)
  5. Spansion 32 MByte QSPI Flash Memory
  6. SI5338A PLL programmable clock generator
  7. TI Low-Dropout Linear Regulator @1.5V
  8. Microchip USB3320 USB-Transceiver
  9. Microchip USB3320 USB-Transceiver

  10. Intersil ISL12020MIRZ Real-Time-Clock

  11. LT Quad 4A PowerSoC DC-DC Converter @1.0V

  12. LT Quad 4A PowerSoC DC-DC Converter @3.3V, @1,8V, @1.2V_MGT, @1.0V_MGT

  13. Samtec ASP-122952-01 160-pin stacking strips (2 rows a 80 positions)
  14. Samtec ASP-122952-01 160-pin stacking strips (2 rows a 80 positions)
  15. Samtec ASP-122952-01 160-pin stacking strips (2 rows a 80 positions)

  16. Micron Technology 4 GByte eMMC

  17. Marvell Alaska 88E1512 Gigabit Ethernet PHY
  18. Marvell Alaska 88E1512 Gigabit Ethernet PHY
    Page break

Key Features

  • Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoC
  • Rugged for shock and high vibration
  • large number of configurable I/Os is provided via rugged high-speed stacking strips
  • Dual ARM Cortex-A9 MPCore
    • 1 GByte RAM (32-Bit wide DDR3)
    • 32 MByte QSPI Flash memory
    • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
    • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
    • 4 GByte eMMC (optional up to 64GByte)
  • 2 x MAC-Address EEPROMs
  • optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM) or optional 2 x 64 MByte HyperFLASH
  • Temperature compensated RTC (real-time clock)
  • Si5338 PLL for GTX Transceiver clocks
  • Plug-on module with 3 x 160-pin high-speed strips
    • 16 GTX high-performance transceiver
    • GT transceiver clock inputs
    • 254 FPGA I/O's (125 LVDS pairs)
  • On-board high-efficiency switch-mode DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
  • User LED

Assembly options for cost or performance optimization available upon request.

Signals, Interfaces and Pins

System Controller CPLD I/O-Pins

Special purpose pins to configure and operate the System Controller CPLD (IC U14) used by TE0782:

NameConnectionNote
CLPD_GPIO7B2BFunction defined by CPLD Firmware (legacy name was BOOTMODE)
CLPD_GPIO6B2BFunction defined by CPLD Firmware (legacy name was CONFIGX)
JTAGENBB2Blogic high enables CPLD JTAG pins, if low CPLD update is disabled
nRST_INB2Bactive low System-reset input (old name RESIN)
CLPD_GPIO0B2BFunction defined by CPLD Firmware
CLPD_GPIO1B2BFunction defined by CPLD Firmware
CLPD_GPIO2B2BFunction defined by CPLD Firmware
CLPD_GPIO3B2BFunction defined by CPLD Firmware
CLPD_GPIO4B2BFunction defined by CPLD Firmware
CLPD_GPIO5B2BFunction defined by CPLD Firmware
CPLD_IOPL 

Small CPLD controls some functions of the SoM, this CPLD can be updated by the end user if support is designed in on customer base.

Boot Modes

TE0782 supports primary boot from

  • SPI Flash

Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).

JTAG Bootmode is always possible no matter the Zynq Boot mode selected.

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JTAG

JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

SignalB2B Pin
TCKJ3:  141
TDIJ3:  147
TDOJ3:  148
TMSJ3:  1142

 

CPLD-JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

SignalB2B Pin
M_TCKJ3:  81
M_TDIJ3:  87
M_TDOJ3:  82
M_TMSJ3:  88
Note

JTAGENB pin in J3 should be kept low or grounded for normal operation.

Clocking

Silabs Multisynth PLL Si5338 can deliver GT reference clocks to all 4 GT Banks. Additionally a GT Reference clock can be generated on the base board for any of the 4 GT Banks. There is reference clock available on the TE0782 for Si5338, optionally external reference clock can be supplied from the base.

ClockFrequencyICZynq PS / PLNotes
PS CLK33.3333 MHzU61PS CLKPS Subsystem main clock
10/100/1000 Mbps ETH PHYs reference25 MHzU11- 
USB PHY reference52 MHzU7- 

PLL reference

25 MHz

U3

-

 

GT REFCLK1

-

B2B connector

BANK110, Pin AC7/AC8

Externally supplied from base

GT REFCLK4

-

B2B connector

BANK111, Pin U7/U8

Externally supplied from base

Si5338 CLK0 U2BANK110, Pin AA8/AA7 
Si5338 CLK1 U2BANK109, Pin AF10/AF9 
Si5338 CLK2 U2BANK111, Pin W8/W7 
Si5338 CLK3 U2BANK112, Pin N8/N7 

Processing System (PS) Peripherals

PeripheralICDesignatorZynq PS / PLMIONotes
QSPI FlashS25FL256SAGBHI20U38PS QSPI0MIO1...MIO6-
ETH0 10/
PeripheralICDesignatorZYNQ PS / PLMIONotesQSPI FlashS25FL256SAGBHI20U38PS QSPI0MIO1...MIO6-ETH0 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U18PS ETH0MIO16...MIO27, MIO52, MIO53-ETH0 10/100/1000 Mbps PHY Reset  PS GPIOMIO7ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESETETH1 10/
100/1000 Mbps PHY88E1512-A0-NNP2I000
U20BANK9, BANK35-PHY
U18PS ETH0MIO16...MIO27, MIO52, MIO53-
ETH0 10/100/1000 Mbps PHY Reset  PS GPIOMIO7ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET
ETH1 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U20BANK9, BANK35-PHY can be used with soft Ethernet MAC IP also
ETH1 10/100/1000 Mbps PHY Reset  BANK35, Pin B15--
USB0USB3320C-EZKU4PS USB0MIO28...MIO39-
USB0 Reset  PS GPIOMIO0OTG_RESET33 (MIO0) -> CPLD -> OTG_RESET
USB1USB3320C-EZKU8USB1MIO40...MIO51-
USB1 Reset  PS GPIOMIO0OTG_RESET33 (MIO0)  -> CPLD -> OTG_RESET
Clock PLLSi5338U2BANK35, Pin L14/L15 Low jitter phase locked loop
 e-MMC (embedded e-MMC)MTFC4GMVEA-4M IT  U15SDIO0MIO10...MIO15-
HyperFlash RAMS26KS512SDPBHI00xU9BANK35-

optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM)

or optional 2 x 64 MByte HyperFLASH

HyperFlash RAMS26KS512SDPBHI00xU12BANK35-as above
EEPROM I2C24LC128-I/STU26BANK35, Pin L14/L15--
EEPROM I2C24AA025E48T-I/OTU22BANK35, Pin L14/L15-MAC Address
EEPROM I2C24AA025E48T-I/OTU24BANK35, Pin L14/L15-MAC Address
RTCISL12020MIRZU17BANK35, Pin L14/L15-Temperature compensated real time clock
RTC InterruptISL12020MIRZU17--RTC_INT -> CPLD

Default MIO mapping

UART  PS UARTMIO8, MIO9forwarded to B2B by SC CPLD

Default MIO mapping

MIO
MIO
Configured asB2BNotes
0USB Reset -CPLD used as level translator
1QSPI0 -SPI Flash-CS
2QSPI0 -SPI Flash-DQ0
3QSPI0 -SPI Flash-DQ1
4QSPI0 -SPI Flash-DQ2
5QSPI0 -SPI Flash-DQ3
6QSPI0 -SPI Flash-SCK
7Ethernet Reset -CPLD used level translator
8
,
UART TX
-
JC3:129output, muxed to B2B by the SC CPLD
 
9UART RX
-
JC3:135input, muxed to B2B by the SC CPLD
 
10SDIO1 D0--
11SDIO1 CMD--
12SDIO1 CLK--
13SDIO1 D1--
14SDIO1 D2--
15SDIO1 D3--
16..27ETH0-Ethernet RGMII PHY
28..39USB0-USB0 ULPI PHY
40...51USB1-USB1 ULPI PHY
52ETH0 MDC--
53ETH0 MDIO--

Pin Definitions

Pins named _vrn and _vrp are connected to ZYNQ PL HP Bank special purpose pins VRN/VRP. If needed they can be connected to DCI calibration resistors on the base. If not, then those pins can be used as general purpose I/O.

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I2C addresses for on-board components

DeviceICDesignatorI2C-AddressNotes
EEPROM24LC128-I/STU260x53user data, parameter
EEPROM24AA025E48T-I/OTU220x50MAC Address/EEPROM
EEPROM24AA025E48T-I/OTU240x51MAC Address/EEPROM
RTCISL12020MIRZU170x6FTemperature compensated real time clock
Battery backed RAMISL12020MIRZU170x57integrated in RTC
PLLSI5338A-B-GMRU20x70 
CPLDLCMXO2-1200HC-4TG100IU14user-

B2B I/O

Number of I/O's connected to the SoC's I/O bank and B2B connector

BankTypeVCCIO MaxConnectorIO countDifferentíalIO VoltageNotes
10HR3.3VJ34422user 
11HR3.3VJ34020user 
12HR3.3VJ24020user 
13HR3.3VJ24020user 
33HP1.8VJ14823user 
34HP1.8VJ14220user 

For detailed information about the pin out, please refer to the Master Pinout Table.

Peripherals

...

LEDs

D1 - Onboard RED LED

Frequency of LED-Toggling [1/2.6sec]Status
1Power problem
2MGT Power problem
3Reset from base board
4FPGA not programmed

This function depend on the CPLD revision.

...

The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11).

ETH1 PHY connection:

PHY PINZYNQ PS / PLSystem Controller CPLDNotes
MDC/MDIOMIO52, MIO53--
LED0BANK35, Pin B12--
LED1BANK35, Pin C12--
InterruptBANK35, Pin A15--
CONFIGBANK35, Pin F14--
RESETn-Pin 53ETH1_RESET33 (MIO7) -> CPLD -> ETH1_RESET
RGMIIMIO16..MIO27 -
MDI--on B2B J2 connector

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ETH2 PHY connection:

PHY PIN
ZYNQ
Zynq PS / PLSystem Controller CPLDNotes
MDC/MDIOBANK35, Pin C17/B17--
LED0BANK35, Pin K15--
LED1BANK35, Pin B16--
InterruptBANK35, Pin A17--
CONFIGBANK35, Pin E15-Pin connected to GND, PHY Address is strapped to 0x00 by default
RESETnBANK35, Pin B15--
RGMIIBANK9--
MDI-

-

-

...

USB

The TE0782 is equipped with two USB PHYs PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHYs PHY's is supplied from an on board 52MHz oscillator (U7).  

USB0 PHY connection:

PHY Pin
ZYNQ
Zynq PS / PLCPLDB2B Name (J2)Notes
ULPIMIO28..39--Zynq USB0 MIO pins are connected to the PHY
REFCLK---52MHz from on board oscillator (U7)
REFSEL[0..2]---000 GND, select 52MHz reference Clock
RESETBMIO0OTG_RESET33-OTG_RESET33 -> CPLD -> OTG_RESET
CLKOUTMIO36--Connected to 1.8V selects reference clock operation mode
DP,DM--USB1_D_P, USB1_D_NUSB Data lines
CPEN--VBUS1_V_ENExternal USB power switch active high enable signal
VBUS--USB1_VBUSConnect to USB VBUS via a series resistor. Check reference schematic
ID--OTG1_IDFor an A-Device connect to ground, for a B-Device left floating

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USB1 PHY connection:

PHY PinZYNQ PS / PLCPLDB2B Name (J2)Notes
ULPIMIO40..51--Zynq USB1 MIO pins are connected to the PHY
REFCLK---52MHz from on board oscillator (U7)
REFSEL[0..2]---000 GND, select 52MHz reference Clock
RESETBMIO0OTG_RESET33-OTG_RESET33 -> CPLD -> OTG_RESET
CLKOUTMIO48--Connected to 1.8V selects reference clock operation mode
DP,DM--USB2_D_P, USB2_D_NUSB Data lines
CPEN--VBUS2_V_ENExternal USB power switch active high enable signal
VBUS--USB2_VBUSConnect to USB VBUS via a series resistor. Check reference schematic
ID--OTG2_IDFor an A-Device connect to ground, for a B-Device left floating

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

...

This RTC IC is supported in Linux so it can be used as hwclock device.

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PLL

The TE0782 is also equipped with a Silicon Labs I2C-programmable clock generator Si5338A (U2). The Si5338 can be programmed using the I2C-bus, to change the frequency on its outputs. It is accessible on the I2C slave address 0x70.

PLL connection:

Input/Output

Default Frequency

Notes

IN1/IN2

Externally supplied

need decoupling on base board

IN3

25MHz

Fixed input clock

CLK0 A/B

-

GT REFCLK0

CLK1 A/B

-

GT REFCLK3

CLK2 A/B

-

GT REFCLK6

CLK3 A/B

-

GT REFCLK5

MAC-Address

...

EEPROM's

Two Microchip 24AA025E48 EEPROMs EEPROM's (U22 and U24) are used on the TE0782. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. Those are accessible by the I2C slave address 0x50 for MAC-Address1 (U22), 0x51 for MAC-Address2 (U24) .

Power

Input Power Supply

Power RailNet nameVoltageI maxNotes
Standby powerC3.3V3.3V100mASystem Control CPLD Power
Main powerVIN12VTBDMain power for all on-board DCDC Regulators

Bank Voltages

BankVoltagemax. Valuenote
03.3 V-FPGA Configuration
5021.5 V-DDR3-RAM Port
109 / 110 / 111 / 1121.2 V-FPGA MGT
500 / 5013.3 V-MIO Banks
91.8 V-ETH2 RGMII
10user3.3 VB2B name: VCCIO_10
11user3.3 VB2B name: VCCIO_11
12user3.3 VB2B name: VCCIO_12
13user3.3 VB2B name: VCCIO_13
33user1.8 VB2B name: VCCIO_33
34user1.8 V
B2B name: VCCIO_34351.8 V-Hyper-RAM, Ethernet, I2C
B2B name: VCCIO_34
351.8 V-Hyper-RAM, Ethernet, I2C

Power-up sequence at start-up

The Trenz TE0782 SoM is equipped with two quad DC/DC-voltage-regulators to generate the required on-board voltages with the values 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT.

There are also additional voltage regulators on board to generate the voltages 1.5V, VTT, VTTREF and 1.8V_MGT.

On this SoM the sequence of powering up of the required on-board voltages is handled internally by the system controller CPLD processing the "POWER GOOD"-signals from the voltage-regulators.

Warning
To avoid any demages to the SoM, check for stabilized on-board voltages in steady state before powering up the SoC's I/O bank voltages VCCIO.

The "POWER GOOD"-signals can be checked on the system controller CPLD.

Pay attention to the voltage level of the I/O-signals, which must not be higher then VCCIO+0.4V.

Initial Delivery state

Storage device nameContentNotes
24LC128-I/ST not programmedUser content

24AA025E48

EEPROMs

EEPROM's

User content not programmed

Valid MAC Address from manufacturer
e-MMC Flash-MemoryEmpty, not programmedExcept serial number programmed by flash vendor

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed

 

SPI Flash main array

demo design

 
HyperFlash RAMnot programmed 

EFUSE USER

Not programmed

 

EFUSE Security

Not programmed

 

Hardware Revision History

Variants Currently In Production

 Module VariantZynq SoC

SoC Junction Temperature

Operating Temperature Range
TE0782-02-035-2IXC7Z035-2FFG900I-40°C to 100°CIndustrial grade
TE0782-02-045-2IXC7Z045-2FFG900I-40°C to 100°CIndustrial grade
TE0782-02-100-2IXC7Z100-2FFG900I-40°C to 100°CIndustrial grade
RevisionChanges

01

Prototypes

02First production release

Technical Specification

Absolute Maximum Ratings

ParameterMinMaxUnitsNotes

Vin supply voltage

-0.3

 

15

V

 

Vin33 supply voltage

-0.

4

5

 

3.75

V

 
VBat supply voltage-
1
0.3
 
6V 
PL IO Bank supply voltage for HR I/O banks (VCCO)-0.53.6V 
I/O input voltage for HP I/O banks-0.55VCCO_X+0.55V 

Voltage on Module JTAG pins

-0.4

VCCO_0+0.55

V

VCCO_0 is 3.3V nominal

Storage Temperature

-40

+85

C

 
Storage Temperature without the ISL12020MIRZ-55+100C 
Note
Assembly variants for higher storage temperature range on request
Note
Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex).

Recommended Operating Conditions

ParameterMinMaxUnitsNotesReference document
Vin supply voltage
  
11.412.6V  
Vin33 supply voltage
  
3.1353.465V  
VBat supply voltage
  
1.85.5V  
PL IO Bank supply voltage for HR I/O banks (VCCO)1.143.465V Xilinx document DS191
I/O input voltage for HR I/O banks
(*)(*)V(*) Check datasheetXilinx document DS191 and DS187      Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 
(*)(*)V(*) Check datasheetXilinx document DS191 and DS187
Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 
Note
Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex).

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Operating Temperature Ranges

Commercial grade modules

All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Industrial grade modules

All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Please download the assembly diagram for exact values.

...

All dimensions are shown in mm. 

Image Modified

Weight

Part

60 g

Plain module

Temperature Ranges

Commercial grade modules

All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Industrial grade modules

View from the BOTTOM of the module.

 

Image Added

View from top onto baseboard for TE0782.

Weight

Weight

Part

60 g

Plain module

Revision History

Hardware Revision History

 RevisionChanges

02

First production release

01Prototypes

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Image AddedAll parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Document Change History

daterevisionauthorsdescription
2017-01-24
Ali Naseri

New numbered pictures describing main components

added variants in production

2016-12-24  Small corrections
2016-06-27v10
initial
Ali Naseri, Jan KumannInitial release

Disclaimer

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