Page History

...

Overview

OnRefer to https://wiki.trenz-electronic.de/display/PD/TE0782-02+TRM thefor online version of this manual and otherthe documentsrest canof beavailable founddocumentation.

The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC . It is equipped with a Xilinx Zynq-7 (XC7Z035, XC7Z045 or XC7Z100).

...

All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options and for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

Block Diagram

Image Removed

Main Components

Image Removed  Image Removed

The SoM TE0782-02 has following components on board:

Key Features

• Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoC

...

Intersil ISL12020MIRZ Real-Time-Clock

...

LT Quad 4A PowerSoC DC-DC Converter @3.3V, @1,8V, @1.2V_MGT, @1.0V_MGT

...

Micron Technology 4 GByte eMMC

...

• Rugged for shock and high vibration
• Large number of configurable I/Os are provided via rugged high-speed stacking strips
• Dual ARM Cortex-A9 MPCore
  • 1 GByte RAM (32-Bit wide DDR3)
  • 32 MByte QSPI Flash memory
  • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
  • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
  • 4 GByte eMMC (optional up to 64 GByte)
• 2 x MAC-address EEPROMs
• Optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte) or optional 2 x 64 MByte HyperFLASH
• Temperature compensated RTC (real-time clock)
• Si5338 PLL for GTX transceiver clocks
• Plug-on module with 3 x 160-pin high-speed strips
  • 16 GTX high-performance transceiver
  • GT transceiver clock inputs
  • 254 FPGA I/O's (125 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Evenly-spread supply pins for good signal integrity
• User LED

Assembly options for cost or performance optimization available upon request.

Block Diagram

Image Added

Main Components

Image Added  Image Added

1. Xilinx Zynq XC7Z SoC (XCZ035, XC7Z045 or XC7Z100), U1
2. Lattice Semiconductor MachXO2 1200HC System Controller CPLD, U14
3. Intelligent Memory 4Gbit DDR3L-1600 SDRAM, U19
4. Intelligent Memory 4Gbit DDR3L-1600 SDRAM, U10
5. Spansion 32 MByte QSPI Flash memory, U38
6. SI5338A PLL programmable clock generator, U2
7. TI low-dropout linear regulator @1.5V, U23
8. Microchip USB3320C USB PHY transceiver, U8
9. Microchip USB3320C USB PHY transceiver, U4

10. Intersil ISL12020MIRZ Real Time Clock, U17

11. LT quad 4A PowerSoC DC-DC converter (1.0V), U13

12. LT quad 4A PowerSoC DC-DC converter (3.3V, 1,8V, 1.2V_MGT, 1.0V_MGT), U16

13. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
14. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
15. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3

16. Micron Technology 4 GByte eMMC, U15

17. Marvell Alaska 88E1512 Gigabit Ethernet PHY, 20
    
18. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18
    

Initial Delivery state

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the SoC's I/O banks and B2B connector:

For detailed information about the pin out, please refer to the Master pin-out table.

JTAG Interface

JTAG access to the Xilinx Zynq device is provided through B2B connector J3.

JTAG access to the System Controller CPLD device is provided through B2B connector J3.

System Controller CPLD I/O Pins

Special purpose pins to configure and operate the System Controller CPLD (IC U14):

Some of the functions of the SoM are controlled by the System Controller CPLD and it's firmware. User can change this by using(creating) different firmware for the System Controller CPLD.

On-board LEDs

Clocking

Silicon Labs PLL Si5338 is used to supply reference clock for MGT banks. Optionally MGT reference clocks can also be supplied from the baseboard for any of the MGT banks. Reference clock for the Si5338 quad clock generator itself can be supplied by the on-board oscillator (U3) or from the baseboard.

Default MIO Mapping

Key Features

• Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoC
• Rugged for shock and high vibration
• large number of configurable I/Os is provided via rugged high-speed stacking strips
• Dual ARM Cortex-A9 MPCore
  • 1 GByte RAM (32-Bit wide DDR3)
  • 32 MByte QSPI Flash memory
  • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
  • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
  • 4 GByte eMMC (optional up to 64GByte)
• 2 x MAC-Address EEPROMs
• optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM) or optional 2 x 64 MByte HyperFLASH
• Temperature compensated RTC (real-time clock)
• Si5338 PLL for GTX Transceiver clocks
• Plug-on module with 3 x 160-pin high-speed strips
  • 16 GTX high-performance transceiver
  • GT transceiver clock inputs
  • 254 FPGA I/O's (125 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Evenly-spread supply pins for good signal integrity
• User LED

Assembly options for cost or performance optimization available upon request.

Signals, Interfaces and Pins

System Controller CPLD I/O-Pins

Special purpose pins to configure and operate the System Controller CPLD (IC U14) used by TE0782:

...

Small CPLD controls some functions of the SoM, this CPLD can be updated by the end user if support is designed in on customer base.

Boot Modes

TE0782 supports primary boot from

• SPI Flash

Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).

JTAG Bootmode is always possible no matter the Zynq Boot mode selected.

JTAG

JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

CPLD-JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

...

Clocking

Silabs Multisynth PLL Si5338 can deliver GT reference clocks to all 4 GT Banks. Additionally a GT Reference clock can be generated on the base board for any of the 4 GT Banks. There is reference clock available on the TE0782 for Si5338, optionally external reference clock can be supplied from the base.

...

PLL reference

...

25 MHz

...

U3

...

-

...

GT REFCLK1

...

-

...

B2B connector

...

BANK110, Pin AC7/AC8

...

Externally supplied from base

...

GT REFCLK4

...

-

...

B2B connector

...

BANK111, Pin U7/U8

...

Externally supplied from base

...

Processing System (PS) Peripherals

...

optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM)

or optional 2 x 64 MByte HyperFLASH

...

Default MIO mapping

Pin Definitions

Pins named _vrn and _vrp are connected to ZYNQ PL HP Bank special purpose pins VRN/VRP. If needed they can be connected to DCI calibration resistors on the base. If not, then those pins can be used as general purpose I/O.

Bank B35 has 100 ohm DCI calibration resistors installed on TE0782, it is also possible to "borrow" the DCI calibration from B35 for banks B34, and B33. For detailed usage of the DCI check Xilinx documentation.

I2C Interface

The on-board I2C components are connected to BANK35, Pin L15 (I2C_SDA) and to BANK35, Pin L14 (I2C_SCL).

I2C addresses for on-board components

...

B2B I/O

Number of I/O's connected to the SoC's I/O bank and B2B connector

For detailed information about the pin out, please refer to the Master Pinout Table.

Peripherals

LEDs

D1 - Onboard RED LED

...

This function depend on the CPLD revision.

D2 - On-board GREEN LED

Green LED connected to MIO8

Ethernet

The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11).

ETH1 PHY connection:

...

ETH2 PHY connection:

...

-

...

USB

The TE0782 is equipped with two USB PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).  

USB0 PHY connection:

...

Gigabit Ethernet

The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11).

ETH1 PHY connection:

ETH2 PHY connection:

USB Interface

The TE0782 is equipped with two USB PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).  

USB0 PHY connection:

USB1 PHY connection:

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

The on-board I²C components are connected to bank 35 pins L15 (I2C_SDA) and L14 (I2C_SCL).

I²C addresses for on-board components:

Pin Definitions

Pins with names ending with _VRN and _VRP are connected to Zynq PL HP bank special purpose pins VRN/VRP and can be routed to DCI calibration resistors on the baseboard. Otherwise they are useable as general purpose I/Os.

Bank 35 has 100 ohm DCI calibration resistors installed, it is also possible to "borrow" the DCI calibration from bank 35 for banks 34 and 33. For more detailed information about the DCI check Xilinx documentation.

On-board peripherals

Processing System (PS) Peripherals

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used for Real Time Clock (U17). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM is at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. 

PLL - Phase Locked Loop

The TE0782 is also equipped with a Silicon Labs programmable clock quad generator Si5338A (U2). The Si5338 is accessible for programming over I²C bus at slave address 0x70.

MAC-Address EEPROM's

Two Microchip 24AA025E48 serial EEPROM's (U22 and U24) are used for storing globally unique 48-bit node addresses,  are compatible with EUI-48(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. EEPROM's are accessible through I²C nus at slave address 0x50 for MAC-Address1 (U22), 0x51 for MAC-Address2 (U24) .

Boot Process

TE0782's primary boot device is on-board SPI Flash. Boot from on-board eMMC is also supported (FSBL must be loaded from SPI Flash).

JTAG boot mode option is always available.

Power and Power-On Sequence

Input Power Supply

Bank Voltages

Power-up sequence at start-up

The Trenz TE0782 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT.

Additional voltage regulators are used to generate voltages 1.5V, VTT, VTTREF and 1.8V_MGT.

Power-on sequence is handled by the System Controller CPLD using power good feedback signals from voltage regulators.

Voltage levels of the I/O signals must not get higher than VCCIO + 0.4V.

USB1 PHY connection:

...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

RTC

An Intersil temperature compensated real time clock IC ISL12020MIRZ is used for timekeeping (U17). Battery voltage must be supplied to the module from the main board.

Battery backed registers are accessed at I2C slave address 0x57.

General purpose RAM is accessed at I2C slave address 0x6F.

This RTC IC is supported in Linux so it can be used as hwclock device.

PLL

The TE0782 is also equipped with a Silicon Labs I2C-programmable clock generator Si5338A (U2). The Si5338 can be programmed using the I2C-bus, to change the frequency on its outputs. It is accessible on the I2C slave address 0x70.

PLL connection:

...

Input/Output

...

Default Frequency

...

Notes

...

Externally supplied

...

need decoupling on base board

...

IN3

...

25MHz

...

Fixed input clock

...

CLK0 A/B

...

-

...

GT REFCLK0

...

CLK1 A/B

...

-

...

GT REFCLK3

...

CLK2 A/B

...

GT REFCLK6

...

CLK3 A/B

...

-

...

GT REFCLK5

MAC-Address EEPROM's

Two Microchip 24AA025E48 EEPROM's (U22 and U24) are used on the TE0782. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. Those are accessible by the I2C slave address 0x50 for MAC-Address1 (U22), 0x51 for MAC-Address2 (U24) .

Power

Input Power Supply

...

Bank Voltages

...

Power-up sequence at start-up

The Trenz TE0782 SoM is equipped with two quad DC/DC-voltage-regulators to generate the required on-board voltages with the values 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT.

There are also additional voltage regulators on board to generate the voltages 1.5V, VTT, VTTREF and 1.8V_MGT.

On this SoM the sequence of powering up of the required on-board voltages is handled internally by the system controller CPLD processing the "POWER GOOD"-signals from the voltage-regulators.

The "POWER GOOD"-signals can be checked on the system controller CPLD.

Pay attention to the voltage level of the I/O-signals, which must not be higher then VCCIO+0.4V.

Initial Delivery state

...

24AA025E48 EEPROM's

...

User content not programmed

...

SPI Flash OTP Area

...

Empty, not programmed

...

Except serial number programmed by flash vendor

...

SPI Flash Quad Enable bit

...

Programmed

...

SPI Flash main array

...

demo design

...

EFUSE USER

...

Not programmed

...

EFUSE Security

...

Not programmed

...

Variants Currently In Production
...
Parameter
Min
Max
Units
Notes
Vin VIN supply voltage
-0.3
15
V
 
Vin33 VIN33 supply voltage
-0.5
3.75
V
 
VBat VBAT supply voltage
-0.3
6
V
 
PL IO Bank supply voltage for HR I/O banks (VCCO)
-0.5
3.6
V
 
I/O input voltage for HP I/O banks
-0.55
VCCO_X+0.55
V
 
Voltage on Module module JTAG pins
-0.4
VCCO_0+0.55
V
VCCO_0 is 3.3V nominal
Storage Temperaturetemperature
-40
+85
C
 
Storage Temperature temperature without the ISL12020MIRZ
-55
+100
C
 
...
Parameter
Min
Max
Units
Notes
Reference document
Vin VIN supply voltage
11.4
12.6
V
 
 
Vin33 VIN33 supply voltage
3.135
3.465
V
 
 
VBat VBAT supply voltage
1.8
5.5
V
 
 
PL IO Bank supply voltage for HR I/O banks (VCCO)
1.14
3.465
V
 
Xilinx document DS191
I/O input voltage for HR I/O banks
(*)
(*)
V
(*) Check datasheet
Xilinx document DS191 and DS187
Voltage on Module JTAG pins
3.135
3.465
V
VCCO_0 is 3.3 V nominal
 
 Note
Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex).
 Page break
Operating Temperature Ranges
Commercial grade modules
All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex).
 Page break
Operating Temperature Ranges
 
Industrial grade: All parts are at least industrial temperature range of -40°C to +85°C.
Module The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
...
Module size: 85 mm × 85 mm.
Mating height with standard connectors: 5 mm
PCB thickness: 1,7 mm
All dimensions are shown in mm.
Image Removed
View from the BOTTOM of the module.
 
Image Removed
View from top onto baseboard for TE0782.
in millimeters.
Image Added
Weight
Weight
Part
60 g
Plain module
...
Hardware Revision History
Date
 Revision
Changes
2015-05-27
02
First production release
 
01
Prototypes
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Image Modified
Document Change History
description12-24
Date
Revision
Contributors
Description
2017-05-23
Jan Kumann
New block diagram.
New product images.
New physical dimensions drawing.
date
revision
authors
2017-01-24
V12
 
Ali Naseri
New numbered pictures describing main components.
added Added variants in production.
2016-
 
 
Small corrections
2016-06-27
v10
Ali Naseri, Jan Kumann
Initial release.
Disclaimer
 Include Page
IN:Legal Notices
IN:Legal Notices