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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

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Table of contents

Table of Contents
outlinetrue

Overview

CPLD Device with designator U21: LCMX02-256HC

Feature Summary

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Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
C_TCK     in30JTAG B2B
C_TDI     in32JTAG B2B
C_TDO     out1JTAG B2B
C_TMS     in29JTAG B2B
EN1       in27Power Enable from B2B Connector (Positive Enable) / currently_not_used
ERR_OUT   in4PS_ERROR_OUT, see ug1085
ERR_STATUSin5PS_ERROR_STATUS, see ug1085
JTAGEN    in26Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
MODE      in25Boot Mode for Zynq/ZynqMP Devices (Flash or SD)
MODE0     out12ZynqMP Boot Mode Pin 0
MODE1     out13ZynqMP Boot Mode Pin 1
MODE2     out14ZynqMP Boot Mode Pin 2
MODE3     out16ZynqMP Boot Mode Pin  3
NOSEQ     inout23/ currently_not_used
PGOOD     out28Module Power Good.
PHY_LED1  in17ETH PHY LED1
TCK     out9JTAG ZynqMP
TDI       out8JTAG ZynqMP
TDO       in10JTAG ZynqMP
TMS       out11JTAG ZynqMP
X0        out20FPGA IO / PHY_LED1
X1        out21FPGA IO / Status

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Boot Mode is selected via B2B Pin Mode. See Table 11.1 Boot Modes from Xilinx ug1085.

ModeDescription
ZeroBoot from SD
OnBoot from Flash

Power

PGOOD is EN1 and not ER_OUT. There is no additional power management.

X0/X1 Pin

PinDescription
X0PHY_LED1
X1ERR_OUT or ERR_STATUS or MODE

 

Appx. A: Change History

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Revision Changes

Document Change History

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
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REV01REV01

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modified-
users
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modified
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document style update
2017-03-06v.2REV01REV01 Revision 01 finished
2017-03-06

v.1

REV01REV01

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created-user
created-user

Initial release
 All  

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modified-users
modified-users

 

Appx. B: Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

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