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some sources available on public doc TEBT0808 TRM

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Template Revision 2.5

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

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Table of Contents

Table of Contents

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The Trenz Electronic TEBT0808 -01 is a testboard test fixture for module TE0808(REV 02 and 03) as well as for TE0803 (REV 01)REV02, REV03) and TE0803(REV01) series.

Refer to http://trenz.org/tebt0808-info for the current online version of this manual and other available documentation.

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Modules
    • TE0808, TE0803
  • On Board
    • Done/Error/Status LEDs
    • MEMS Oscillator 125.00 MHz
    • Boot Mode DIP-Switch
    • 2x DIP-Switches to control TE080x power domains
  • Interface
    • Pin
  • Accepts TE0808 / TE0803
  • Single 3.3V input
    • Header for TE0790 JTAG/UART Adapter
    20 Pin
    • ARM JTAG header
    (connected to MIO JTAG 0)
  • 10 Pin I2C header for Silabs Clock Builder Field Programmer
    • Pin Header for I2C
    • Board to Board (B2B) Connectors
    Done, Error/Status LEDs
    • One PL GT with 4x SMA
    connectors
    • Connectors
    • One PS GT with 4x SMA
    connectors
  • GT local loopback
  • PL I/O loopbacks
  • PS I/O loopbacks
  • Boot Mode switches
  • Power control switches to control TE0808 power domains
    • Connectors
    • One pre-assembled TE0790 XMOD FTDI JTAG adapter

Supported Bootmodes are SPI and JTAG.

  • Power:
    • 3.3 V (Nominal Supply Voltage)
  • Dimension: 90mm x 90mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Main Components

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  1. Uninsulated 2 mm rigid socket. J8-J7Power Jack. J7-J8
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. Box Headers, Straight/Angled J5-J16
  5. ARM PJTAG Pin Header J16
  6. I2C Pin Header, J5
  7. Board to Board ConnectorsBoard to Board Connector. J1...4
  8. Clock MEMS Oscillator, U2
  9. On-Board LEDLEDs, D2...4
  10. DIP-Switch, S1...3
  11. XMOD JTAG Baseheader,  JX1

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

-

-

-


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

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titleBoot processProcess.

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M3M2M1M0Bootmode
Hex
BootmodeNotes
ONONONON
0x0
0b0000PS Main JTAG (TE0790 USB JTAG)
Needed for SPI Flash Programming
DIPs are inverted
ONONOFFON
0x2
0b0010SPI Flash (dual parallel, 4bit x 2, 32bit Addressing)
Default
DIPs are inverted
OFFONONON0b1000PJTAG(MIO29:26)DIPs are inverted



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Signal

B2BNote

PLL_RST

J2-89
SRST_BJ2-96connected Connected to PJTAG0_SRST - J16


Signals, Interfaces and Pins

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Board to Board (B2B) I/Os

FPGA bank number and number TEBT0808 has four B2B Connectors and each connector has 160 pins. Number of I/O signals and Interfaces connected to the B2B connectorconnectors is as following table:

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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O
22 singel ended, 11

46 Single Ended, 23 Differential

8 singel ended, 4

16 Single Ended, 8 Differential

8 singel ended, 4

16 Single Ended, 8 Differential

8 singel ended, 4 Differential

3 singel ended

Connected to Bank 66

Connected to Bank 228

Connected to Bank 229

Connected to Bank 230

VCCO_66,

16 Single Ended, 8 Differential

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

PL_1V8

J2
Ethernet PHY

32 singel ended, 16 Differential

4 singel ended, 16 Differential

Connected to Bank 505

Connected to Bank 128

Control Signals

User IO

28 Single Ended, 14 Differential

6 Single Ended, 3 Differential

IOs are Loop-Back

IOs are Loop-Back

Boot Mode 4 Single EndedMODE0...3
Control Signals25 Single Ended
15 single ended

PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE

Power Control Signal10 single endedEN

EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L

JTAG Interface7
single ended
Single EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
WANNE2
I22
single ended
Single EndedPLL_SCL, PLL_SDA
Clock

6

singel ended

Single Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User
I/O

12 singel ended, 6 Differential

12 singel ended, 6
IO

24 Single Ended, 12 Differential

24 Single Ended, 12 Differential

Connected to Module FPGA, Bank 48

Connected to Module FPGA, Bank 47

Clock6
singel ended
Single Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface
7 single ended
4 Single EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO
27 single endedMIO19
45 Single EndedMIO13..
76
77
UART2
single ended
Single EndedTXD, RXD
Power
pins
Control Signals4
single ended
Single EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3
J4User I/O

48 Single Ended, 24 Differential

48

singel ended

Single Ended,

62

24 Differential

4 single ended

Connected to Bank 64

4 Single Ended

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

B64_T0...3

B65_T0...3

Connected to Bank 64

Power pins4
single ended
Single EndedVCCO_64, VCCO65

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SMA Coaxial Connectors

TEBT0808 is equipped with 8 SMD Coaxial Connectors. JTAG access to the TE0803 or TE0808 SoM through B2B connector JM2.

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Designator 
JTAG Signal
SchematicB2B Connector
TMS
Notes
J2-126
TDIJ2-122
TDOJ2-124
TCK

J2-120

MRJ2-83
RXDJ3-141
TXDJ3-139

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Notes :

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J6B230_TX3_PJ1
J9B230_RX3_NJ1
J10B230_RX3_PJ1
J11B230_TX3_PJ1
J12B505_TX0_NJ2
J13B5050TX0_PJ2
J14B505_RX0_NJ2
J15B505_RX0_PJ2


XMOD JTAG

JTAG access to the TEBT080X  is available through B2B connector JB2 using XMOD adapter TE0790.

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JTAG Signal

B2B Connector

Chip/Interface

Notes

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TMSJ2- 126
TDIJ2- 122
TDOJ2- 124
TCKJ2- 120


The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) on TE0790 can be configured by the DIP-switch S2 which must be set as following. 

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There are thre DIP Switches, S1, S2, S3.

The Boot Mode can be set through DIP Switch S1, refer to BootMode table.

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Signals

B2B

S1 switchNotes
MODE0J2-109S1AMODE1J2-107S1BMODE2J2-105S1CMODE3J2-103S1D

Control signals must be set by DIP Switch S2, S3.

DIP Switch,S2DefaultDescription
1ONUpdate Mode JTAG access to SC CPLD only
2OFFMust be always in OFF state.
3OFFVIO is supplied from Module
4OFF3.3V is supplied by the carrier TEBT0808


PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JB3.

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Signals

JTAG Signal

B2B Connector

S2 switch
Notes
EN
PJTAG_
PSGT
TMS
J2-84S2AEN_GT_RJ2-95S2BEN_GT_LJ2-97S2CEN_PLL_PWRJ2-77S2Dconnected to PG_PL
J3- 94
PJTAG_TDIJ3- 90
PJTAG_TDOJ3- 92
PJTAG_TCKJ3- 88
PJTAG_SRSTJ2- 96Connected to SRST_B