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some sources available on public doc TEBT0808 TRM

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Template Revision 2.5

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

...

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Download PDF version of this document.


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Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...TEBT0808 is a test fixture for module TE0808(REV02, REV03) and TE0803(REV01) series.

Refer to http://trenz.org/tec0850tebt0808-info for the current online version of this manual and other available documentation.

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Notes :

...

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • ...
  • ....
  • ....

Block Diagram

...

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

...

anchorFigure_OV_BD
titleTExxxx block diagram
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  • Modules
    • TE0808, TE0803
  • On Board
    • Done/Error/Status LEDs
    • MEMS Oscillator 125.00 MHz
    • Boot Mode DIP-Switch
    • 2x DIP-Switches to control TE080x power domains
  • Interface
    • Pin Header for TE0790 JTAG/UART Adapter
    • ARM JTAG header
    • Pin Header for I2C
    • Board to Board (B2B) Connectors
    • One PL GT with 4x SMA Connectors
    • One PS GT with 4x SMA Connectors
    • One pre-assembled TE0790 XMOD FTDI JTAG adapter
  • Power:
    • 3.3 V (Nominal Supply Voltage)
  • Dimension: 90mm x 90mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .



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titleTEBT0808 Block Diagram


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Main Components

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Notes :

Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


...

Scroll Title
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titleTExxxx main componentsTEBT0808 Main Components


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  1. ...
  2. ...
  3. ...

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

...

anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

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  1. Uninsulated Power Jack. J7-J8
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. ARM PJTAG Pin Header J16
  5. I2C Pin Header, J5
  6. Board to Board Connectors. J1...4
  7. MEMS Oscillator, U2
  8. On-Board LEDs, D2...4
  9. DIP-Switch, S1...3
  10. XMOD header, JX1

Initial Delivery State

...

Storage device name

...

Content

...

Notes

...

Quad SPI Flash

...

Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.
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titleBoot process.
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MODE Signal State

Boot Mode

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


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titleReset process.Initial delivery state of programmable devices on the module

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Signal

Storage device name

B2BI/ONote

...

Content

Notes

-

-

-


Configuration Signals

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

...

anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

...

  • Overview of Boot Mode, Reset, Enables.

Boot mode can be set by DIP-Switch S1.

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titleBoot Process.

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M3M2M1M0BootmodeBootmodeNotes
ONONONON0b0000PS Main JTAG (TE0790 USB JTAG)DIPs are inverted
ONONOFFON0b0010SPI Flash (dual parallel, 4bit x 2, 32bit Addressing)DIPs are inverted
OFFONONON0b1000PJTAG(MIO29:26)DIPs are inverted



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titleJTAG pins connectionReset Process.

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JTAG

Signal

B2B
Connector
TMS
Note
TDITDOTCKJTAG_EN

...

PLL_RST

J2-89
SRST_BJ2-96Connected to PJTAG0_SRST - J16


Signals, Interfaces and Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

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MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

TEBT0808 has four B2B Connectors and each connector has 160 pins. Number of I/O signals and Interfaces connected to the B2B connectors is as following table:

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titleGeneral PL I/O to B2B connectors information
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titleMIOs pins

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MIO PinConnected to
B2B Connector
Notes

...

InterfacesNumber of I/ONotes
J1

User I/O

46 Single Ended, 23 Differential

16 Single Ended, 8 Differential

16 Single Ended, 8 Differential

16 Single Ended, 8 Differential

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

PL_1V8

J2

User IO

28 Single Ended, 14 Differential

6 Single Ended, 3 Differential

IOs are Loop-Back

IOs are Loop-Back

Boot Mode 4 Single EndedMODE0...3
Control Signals25 Single Ended

PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE, EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L

JTAG Interface7 Single EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
I2C 2 Single EndedPLL_SCL, PLL_SDA
Clock

6 Single Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User IO

24 Single Ended, 12 Differential

24 Single Ended, 12 Differential

Connected to Module FPGA, Bank 48

Connected to Module FPGA, Bank 47

Clock6 Single Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface4 Single EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO45 Single EndedMIO13..77
UART2 Single EndedTXD, RXD
Power Control Signals4 Single EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3
J4User I/O

48 Single Ended, 24 Differential

48 Single Ended, 24 Differential

4 Single Ended

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

B64_T0...3

B65_T0...3

Power pins4 Single EndedVCCO_64, VCCO65


SMA Coaxial Connectors

TEBT0808 is equipped with 8 SMD Coaxial Connectors. 

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titleSMD Coaxial Connectors
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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

...

anchorTable_OBP
titleOn board peripherals

...

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

...

anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

...

anchorTable_OBP_RTC
titleI2C interface MIOs and pins

...

anchorTable_OBP_I2C_RTC
titleI2C Address for RTC

...

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titleI2C EEPROM interface MIOs and pins
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MIO PinSchematicU?? PinNotes
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titleI2C address for EEPROM

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MIO Pin
Designator 
I2C Address
Schematic
Designator
B2B ConnectorNotes

LEDs

...

anchorTable_OBP_LED
titleOn-board LEDs
J6B230_TX3_PJ1
J9B230_RX3_NJ1
J10B230_RX3_PJ1
J11B230_TX3_PJ1
J12B505_TX0_NJ2
J13B5050TX0_PJ2
J14B505_RX0_NJ2
J15B505_RX0_PJ2


XMOD JTAG

JTAG access to the TEBT080X  is available through B2B connector JB2 using XMOD adapter TE0790.

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titleJTAG Pins Connection

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JTAG Signal

B2B Connector

Notes
TMSJ2- 126
TDIJ2- 122
TDOJ2- 124
TCKJ2- 120


The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) on TE0790 can be configured by the DIP-switch S2 which must be set as following. 

...

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

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titleEthernet PHY to Zynq SoC connections Xmod Adapter DIP-Switch Setting Description

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BankSignal NameETH1ETH2Signal Description

...

DIP Switch,S2DefaultDescription
1ONUpdate Mode JTAG access to SC CPLD only
2OFFMust be always in OFF state.
3OFFVIO is supplied from Module
4OFF3.3V is supplied by the carrier TEBT0808


PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JB3.

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titleCAN Tranciever interface MIOsPJTAG Pins Connection

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Bank

JTAG Signal

SchematicU?? PinNotesD-TxDriver InputR-RxReciever Output

...

B2B Connector

Notes
PJTAG_TMSJ3- 94
PJTAG_TDIJ3- 90
PJTAG_TDOJ3- 92
PJTAG_TCKJ3- 88
PJTAG_SRSTJ2- 96Connected to SRST_B


Pin header

The I2C signals can be accessed through pin header J5.

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titleI2C Connections

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titleOsillators

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Designator

Signals

Description

B2B Connector

Frequency
Pin Header
Note
Notes
MHzMHzKHz

Power and Power-On Sequence

...

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

PLL_SCLJ2- 90J5- 3
PLL_SDAJ2- 92J5- 7


Test Points

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titleTest Points Information

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Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

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titlePower Consumption

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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

...

anchorFigure_PWR_PD
titlePower Distribution
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Power-On Sequence

...

anchorFigure_PWR_PS
titlePower Sequency
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Voltage Monitor Circuit

...

anchorFigure_PWR_VMC
titleVoltage Monitor Circuit
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Power Rails

...

anchorTable_PWR_PR
titleModule power rails.

...

B2B Connector

JM1 Pin

...

B2B Connector

JM2 Pin

...

B2B Connector

JM3 Pin

...

Bank Voltages

...

anchorTable_PWR_BV
titleZynq SoC bank voltages.

...

Bank          

...

Voltage

...

hiddentrue
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...

use "include page" macro and link to the general B2B connector page of the module series,

...

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

  • 3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

    Operating Temperature: -??°C ~ ??°C
    Current Rating: ??A per ContactNumber of Positions: ??
    Number of Rows: ??

Technical Specifications

Absolute Maximum Ratings

...

anchorTable_TS_AMR
titlePS absolute maximum ratings

...

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

...

anchorTable_TS_ROC
titleRecommended operating conditions.

...

Physical Dimensions

  • Module size: ?? mm × ?? mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ? mm.

PCB thickness: ?? mm.

...

hiddentrue
idComments

In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Test Point

Signals

B2B Connector

Notes
TP 1DDR_1V2J2-135
TP 2PG_PSGTJ2-82
TP 3ERR_STATUSJ2-86
TP 4PLL_FDECJ2-94
TP 5EN_LPDJ2-108
TP 6EN_DDRJ2-112
TP 7PG_PLJ2-104
TP 8PG_PLL_1V8J2-80
TP 9N_PSGTJ2-84
TP 10ERR_OUTJ2-88
TP 11EN_FPDJ2-102
TP 12LP_GOODJ2-106
TP 13PG_FPDJ2-110
TP 14PG_DDRJ2-114
TP 15EN_PLL_PWRJ2-77
TP 16PLL_FINCJ2-81
TP 17PG_GT_RJ2-91
TP 18EN_GT_RJ2-95
TP 19EN_PLJ2-101
TP 20EN_GT_LJ2-79
TP 21PLL_SEL0J2-93
TP 22PG_GT_LJ2-97
TP 23INIT_BJ2-98
TP 24IN1_PJ2-4
TP 25PLL_SEL1J2-87
TP 26PLL_LOLNJ2-85
TP 27PLL_RSTJ2-89
TP 28DX_PJ2-119
TP 29DX_NJ2-121
TP 30IN1_NJ2-6
TP 31B505_CLK0_PJ2-10
TP 32B505_CLK0_NJ2-12
TP 33B505_CLK1_PJ2-16
TP 34B505_CLK1_NJ2-18
TP 35B128_CLK1_PJ2-22
TP 36B128_CLK1_NJ2-24
TP 37CLK0_NJ2-1
TP 38CLK0_PJ2-3
TP 39CLK8_PJ2-7
TP 40CLK8_NJ2-9
TP 41CLK7_PJ2-13
TP 42CLK7_NJ2-15
TP 43IN2_PJ3-66
TP 44IN2_NJ3-68
TP 45B230_CLK1_NJ3-59
TP 46B230_CLK1_PJ3-61
TP 47B229_CLK0_NJ3-65
TP 48B229_CLK0_PJ3-67
TP 49PLL_3V3J3-152
TP 50GNDJ3-155
TP 51PL_1V8J1-121
TP 52PS_1V8J3-147
TP 53SI_PLL_1V8J3-151
TP 54PROG_BJ2-100
TP 55...56GND-


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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titleOn Board Peripherals

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Chip/InterfaceDesignatorNotes
DIP SwitchS1...3
LEDsD2...4Red LEDs
OscillatorU2125.00 MHz


DIP Switch

There are three DIP Switches, S1, S2, S3.

The Boot Mode can be set through DIP Switch S1, refer to BootMode table.

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titleDIP Switch S1

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DIP Switch S1Signals

B2B

Notes
S1AMODE0J2-109
S1BMODE1J2-107
S1CMODE2J2-105
S1DMODE3J2-103


Control signals must be set using DIP Switch S2, S3.

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titleDIP Switch S2

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DIP Switch S2SignalsB2BNotes
S2AEN_PSGTJ2-84Position OFF enables power rail
S2BEN_GT_RJ2-95Position OFF enables power rail
S2CEN_GT_LJ2-97Position OFF enables power rail
S2DEN_PLL_PWRJ2-77Position OFF enables power rail, connected to PG_PL



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titleDIP Switch S3

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DIP Switch S3SignalsB2BS3 switchNotes
S3AEN_DDRJ2-112S3APosition OFF enables power rail
S3BEN_LPDJ2-108S3BPosition OFF enables power rail
S3CEN_PLJ2-101S3CPosition OFF enables power rail
S3DEN_FPDJ2-102S3DPosition OFF enables power rail


LEDs

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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D2RedDONEActive HighNon User LED
D3RedERR_STATUSActive HighNon User LED
D4RedERR_OUTActive HighNon User LED


Clock Sources

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titleOsillators

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DesignatorDescriptionFrequencyNote
U2MEMS Oscillator125.00 MHz


Power and Power-On Sequence

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hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Scroll Title
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titlePower Consumption

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2,0mm MC LB2Note
J73.3V direct modules power supply
J8GND


Power Consumption

Minimum current depends mainly on design and cooling solution. Use Xilinx Power Estimator and/or Your Vivado Project to estimate min current. Minimum of 3A are recommanded for basic functionality.

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titlePower Consumption

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Power Input PinTypical Current
3.3VTBD*


* TBD - To Be Determined

Power Distribution Dependencies

Input oower sourced directly the module, Only one Diode D1 is used for inverse polarity protection.

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titlePower Distribution


Scroll Ignore

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Power Rails

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Power Rail Name

B2B J1 PinsB2B J2 PinsB2B J3 Pins

Directions

Note
PL_DCIN151, 153, 155, 157, 159--Output-
DCDCIN

-

154, 156, 158, 160,
153, 155, 157, 159

-Output-
LP_DCDC-138, 140, 142, 144-Output-
PS_BATT-125-Output-
GT_DCDC--157, 158, 159, 160Output-
PLL_3V3--152Output-
SI_PLL_1V8--151Input-
PS_1V8-99147, 148Input-
PL_1V891, 121--Input-
DDR_1V2-135-Input-


Board to Board Connectors

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  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    6 x 6 SoM LSHM B2B Connectors
    6 x 6 SoM LSHM B2B Connectors

Include Page
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors
5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

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SymbolsMinMaxUnitNote
VIN-0.34V

VIN is connected directly to module

Storage Temperatur-40+85°CSee DIP Switch, CHS-04TA datasheet


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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titleRecommended operating conditions.

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SymbolsMinMaxUnitNote
VIN3,143.47VCheck also TRM of the connected module
Operating Temperatur-40+85°C


Physical Dimensions

  • Module size: 90 mm × 90 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 3.5 mm.

PCB thickness: 1.6 mm.

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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



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titlePhysical Dimension


Scroll Ignore

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scroll-htmltrue

Image Added


Currently Offered Variants 

Page properties
hiddentrue
idComments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

if not available, set.


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titleTrenz Electronic Shop Overview

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Trenz shop TEBT0808 overview page
English pageGerman page


Revision History

Hardware Revision History

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DateRevisionChangesDocumentation Link
2016-05-3001Initial ReleaseREV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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titleBoard hardware revision number.


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Image Added

...

anchorFigure_TS_PD
titlePhysical Dimension
Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Currently Offered Variants 

Page properties
hiddentrue
idComments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

if not available, set.

...

anchorTable_VCP_SO
titleTrenz Electronic Shop Overview

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Revision History

Hardware Revision History

-
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DateRevisionNotePCN
-


Document Change History

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hiddentrue
idComments
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports

...

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titleDocument change history.

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DateRevisionContributorDescription

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change list

  • Updated block diagram
2020-05-11v.54John Hartfiel

  • add notes to DIP section

  • Correction on configuration signal section
2020-01-24v.49Pedram Babakhani
  • Initial Release

--

all

Edit

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices

...