Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.


some sources available on public doc TEBT0808 TRM

Page properties
hiddentrue
idComments

Template Revision 2.5

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

...

The Trenz Electronic TEBT0808 -01 is a testboard test fixture for module TE0808(REV 02 and 03) as well as for TE0803 (REV 01)REV02, REV03) and TE0803(REV01) series.

Refer to http://trenz.org/tebt0808-info for the current online version of this manual and other available documentation.

...

Page properties
hiddentrue
idComments

Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Modules
    • TE0808, TE0803
  • On Board
    • Done/Error/Status LEDs
    • MEMS Oscillator 125.00 MHz
    • Boot Mode DIP-Switch
    • 2x DIP-Switches to control TE080x power domains
  • Interface
    • Pin
  • Accepts TE0808 / TE0803
  • Single 3.3V input
    • Header for TE0790 JTAG/UART Adapter
    20 Pin
    • ARM JTAG header
    (connected to MIO JTAG 0)
  • 10 Pin I2C header for Silabs Clock Builder Field Programmer
    • Pin Header for I2C
    • Board to Board (B2B) Connectors
    Done, Error/Status LEDs
    • One PL GT with 4x SMA
    connectors
    • Connectors
    • One PS GT with 4x SMA
    connectors
  • GT local loopback
  • PL I/O loopbacks
  • PS I/O loopbacks
  • Boot Mode switches
  • Power control switches to control TE0808 power domains
    • Connectors
    • One pre-assembled TE0790 XMOD FTDI JTAG adapter

Supported Bootmodes are SPI and JTAG.

  • Power:
    • 3.3 V (Nominal Supply Voltage)
  • Dimension: 90mm x 90mm

Block Diagram

Page properties
hiddentrue
idComments

add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


...

Scroll Title
anchorFigure_OV_BD
titleTEBT0808 block diagramBlock Diagram


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision1123
diagramNameTEBT0808_OV_BD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth640636



Scroll Only

Image Modified


Main Components

...

Scroll Title
anchorFigure_OV_BD
titleTEBT0808 main componentsMain Components


Scroll Ignore

draw.io Diagram
bordertruefalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision4
diagramNameTEBT0808_OV_MC
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth640
revision3


Scroll Only

Image Modified


  1. Uninsulated 2 mm rigid socket. J8-J7Power Jack. J7-J8
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. Box Headers, Straight/Angled J5-J16
  5. ARM PJTAG Pin Header J16
  6. I2C Pin Header, J5
  7. Board to Board ConnectorsBoard to Board Connector. J1...4
  8. Clock MEMS Oscillator, U2
  9. On-Board LEDLEDs, D2...4
  10. DIP-Switch, S1...3
  11. XMOD JTAG Baseheader,  JX1

Initial Delivery State

Page properties
hiddentrue
idComments

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

...

Scroll Title
anchorTable_OV_BP
titleBoot processProcess.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

M3M2M1M0Bootmode HexBootmodeNotes
ONONONON0x00b0000PS Main JTAG (TE0790 USB JTAG)Needed for SPI Flash ProgrammingDIPs are inverted
ONONOFFON0x20b0010SPI Flash (dual parallel, 4bit x 2, 32bit Addressing)DefaultDIPs are inverted
OFFONONON0b1000PJTAG(MIO29:26)DIPs are inverted



Scroll Title
anchorTable_OV_RST
titleReset processProcess.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

B2BNote

PLL_RST

J2-89
SRST_BJ2-96connected Connected to PJTAG0_SRST - J16


Signals, Interfaces and Pins

...

Board to Board (B2B) I/Os

FPGA bank number and number TEBT0808 has four B2B Connectors and each connector has 160 pins. Number of I/O signals and Interfaces connected to the B2B connectorconnectors is as following table:

Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O

22 singel ended, 11 46 Single Ended, 23 Differential8 singel ended, 4

16 Single Ended, 8 Differential8

singel ended, 4 16 Single Ended, 8 Differential

8 singel ended, 4 Differential

3 singel ended

16 Single Ended, 8 Differential

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

Connected to Bank 66

Connected to Bank 228

Connected to Bank 229

Connected to Bank 230

VCCO_66, PL_1V8

J2
Ethernet PHY

32 singel ended, 16 Differential

4 singel ended, 16 Differential

Connected to Bank 505

Connected to Bank 128


User IO

28 Single Ended, 14 Differential

6 Single Ended, 3 Differential

IOs are Loop-Back

IOs are Loop-Back

Boot Mode 4 Single EndedMODE0...3
Control Signals25 Single EndedControl Signals15 single ended

PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE

Power Control Signal10 single ended

EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L

JTAG Interface7 single endedSingle EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
WANNE2I22 single endedSingle EndedPLL_SCL, PLL_SDA
Clock

6 singel endedSingle Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User I/OIO

24 Single Ended, 12 Differential

24 Single Ended, 12

12 singel ended, 6 Differential

12 singel ended, 6 Differential

Connected to Module FPGA, Bank 48

Connected to Module FPGA, Bank 47

Clock6 singel endedSingle Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface7 single ended4 Single EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO27 single ended45 Single EndedMIO13MIO19..7677
UART2 single endedSingle EndedTXD, RXD
Power pinsControl Signals4 single endedSingle EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3
J4User I/O

48 singel ended, 62 Differential

4 single ended

Single Ended, 24 Differential

48 Single Ended, 24 Differential

4 Single Ended

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

B64_T0...3

B65_T0...3

Connected to Bank 64

Connected to Bank 64

Power pins4 single endedSingle EndedVCCO_64, VCCO65

...


SMA Coaxial Connectors

TEBT0808 is equipped with 8 SMD Coaxial Connectors. JTAG access to the TE0803 or TE0808 SoM through B2B connector JM2.

Scroll Title
anchorTable_SIP_JTGSMDCoax
titleJTAG pins connectionSMD Coaxial Connectors

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Designator 
JTAG Signal
SchematicB2B Connector
TMSJ2-126
TDIJ2-122
TDOJ2-124
TCK

J2-120

MRJ2-83
RXDJ3-141
TXDJ3-139

On-board Peripherals

Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
Page properties
hiddentrue
idComments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Notes
J6B230_TX3_PJ1
J9B230_RX3_NJ1
J10B230_RX3_PJ1
J11B230_TX3_PJ1
J12B505_TX0_NJ2
J13B5050TX0_PJ2
J14B505_RX0_NJ2
J15B505_RX0_PJ2


XMOD JTAG

JTAG access to the TEBT080X  is available through B2B connector JB2 using XMOD adapter TE0790.

Designator
Scroll Title
anchorTable_SIP_OBPJTG
titleOn board peripheralsJTAG Pins Connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

B2B Connector

Chip/Interface

Notes
Oscillator
TMS
U2125.00 MHz

...

J2- 126
TDIJ2- 122
TDOJ2- 124
TCKJ2- 120


The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) on TE0790 can be configured by the DIP-switch S2 which must be set as following. 

Scroll Title
anchorTable_SIP_Xmod_DIP
title Xmod Adapter DIP-Switch Setting Description

Scroll Table Layout
orientationportrait

There are thre DIP Switches, S1, S2, S3.

The Boot Mode can be set through DIP Switch S1, refer to BootMode table.

Scroll Title
anchorTable_OBP_DIP
titleDIP Switch S1

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signals

B2B

S1 switchNotes
MODE0J2-109S1AMODE1J2-107S1BMODE2J2-105S1CMODE3J2-103S1D

...

DIP Switch,S2DefaultDescription
1ONUpdate Mode JTAG access to SC CPLD only
2OFFMust be always in OFF state.
3OFFVIO is supplied from Module
4OFF3.3V is supplied by the carrier TEBT0808


PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JB3.

Scroll Title
anchorTable_OBPSIP_DIPJTG
titleDIP Switch S2PJTAG Pins Connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signals

JTAG Signal

B2B

S2 switch

Connector

Notes
EN
PJTAG_
PSGT
TMS
J2-84S2AEN_GT_RJ2-95S2BEN_GT_LJ2-97S2C
EN_PLL_PWRJ2-77S2Dconnected to PG_PL
J3- 94
PJTAG_TDIJ3- 90
PJTAG_TDOJ3- 92
PJTAG_TCKJ3- 88
PJTAG_SRSTJ2- 96Connected to SRST_B


Pin header

The I2C signals can be accessed through pin header J5.

EN_PL
scroll-scroll-title
anchorTable_OBPSIP_DIPI2C
titleDIP Switch S3I2C Connections

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signals

B2B Connector

S3 switch
Pin HeaderNotes
EN
PLL_
DDR
SCLJ2-
112
90J5- 3
PLL_SDA
S3AEN_LPDJ2-108S3B
J2-
101S3CEN_FPDJ2-102S3D