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The Trenz Electronic TEBT0808 is a test fixture for module TE0808(REV01REV02, REV02REV03) and TE0803(REV01) series.

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Modules
    • TE0808, TE0803
  • On Board
    • Done/Error/Status LEDs
    • MEMS Oscillator 125.00 MHz
    • Boot Mode DIP-Switch
    • 2x DIP-Switches to control TE080x power domains
  • InterfaceSingle 3.3V input (Direct modules power supply)
    • Pin Header for TE0790 JTAG/UART Adapter
    20 Pin
    • ARM JTAG header
    (connected to MIO JTAG 0)
    10
    • Pin
    I2C header for Silabs Clock Builder Field ProgrammerDone/Error/Status LEDs
    • Header for I2C
    • Board to Board (B2B) Connectors
    • One PL GT with 4x SMA Connectors
    • One PS GT with 4x SMA Connectors
  • GT local loopback
  • PL I/O loopbacks
  • PS I/O loopbacks
  • Boot Mode DIP Switch
  • Power control switches to control TE080x power domains
    • One pre-assembled TE0790 XMOD FTDI JTAG adapter

Supported Bootmodes are SPI and JTAG.

  • Power:
    • 3.3 V (Nominal Supply Voltage)
  • Dimension: 90mm x 90mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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titleTEBT0808 Block Diagram


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borderfalse
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fitWindowfalse
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linksauto
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diagramWidth640636



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Main Components

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titleTEBT0808 Main Components


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borderfalse
viewerToolbartrue
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linksauto
tbstylehidden
diagramWidth640


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  1. Non-insulated Uninsulated Power Jack. J7-J8-J7
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. Box Headers, Straight/Angled J5-J16
  5. ARM PJTAG Pin Header J16
  6. I2C Pin Header, J5
  7. Board to Board ConnectorConnectors. J1...4
  8. Clock MEMS Oscillator, U2
  9. On-Board LEDs, D2...4
  10. DIP-Switch, S1...3
  11. XMOD JTAG Baseheader, JX1

Initial Delivery State

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titleBoot Process.

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ON
M3M2M1M0Bootmode HexBootmodeNotes
ONONONON0xF0b0000PS Main JTAG (TE0790 USB JTAG)DIPs are inverted
ONONOFFON0xD0b0010SPI Flash (dual parallel, 4bit x 2, 32bit Addressing)DIPs are inverted
OFFONOFFONOFFON0x80b1000PJTAG(MIO29:26)DIPs are inverted



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titleReset Process.

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Signal

B2BNote

PLL_RST

J2-89
SRST_BJ2-96Connected to PJTAG0_SRST - J16


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Board to Board (B2B) I/Os

FPGA bank number and number TEBT0808 has four B2B Connectors and each connector has 160 pins. Number of I/O signals and Interfaces connected to the B2B connectorconnectors is as following table:

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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O

22 46 Single Ended, 11 23 Differential

8 16 Single Ended, 4 8 Differential8

16 Single Ended, 4 8 Differential8

16 Single Ended, 4 8 Differential

3 4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

Connected to Bank 66

Connected to Bank 228

Connected to Bank 229

Connected to Bank 230

VCCO_66, PL_1V8

J2

Ethernet PHY

User IO

32 28 Single Ended, 16 14 Differential

4 6 Single Ended, 16 3 Differential

Connected to Bank 505

Connected to Bank 128

IOs are Loop-Back

IOs are Loop-Back

Boot Mode 4 Single EndedMODE0...3
Control Signals25 Single Ended

PLL_

Control Signals15 Single EndedPLL_

SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE

Power Control Signal10 Single Ended

, EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L

JTAG Interface7 Single EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
WANNE2I2C 2 Single EndedPLL_SCL, PLL_SDA
Clock

6 Single Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User I/OIO

12 24 Single Ended, 6 12 Differential

12 24 Single Ended, 6 12 Differential

Connected to Module FPGA, Bank 48

Connected to Module FPGA, Bank 47

Clock6 Single Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface7 4 Single EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO27 45 Single EndedMIO19MIO13..7677
UART2 Single EndedTXD, RXD
Power pinsControl Signals4 Single EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3
J4User I/O

48 Single Ended, 62 24 Differential

4 48 Single Ended

Connected to Bank 64

Connected to Bank 64

, 24 Differential

4 Single Ended

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

B64_T0...3

B65_T0...3

Power pins4 Single EndedPower pins4 Single EndedVCCO_64, VCCO65

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SMA Coaxial Connectors

TEBT0808 is equipped with 8 SMD Coaxial Connectors. JTAG access to the TEBT080X  is available through B2B connector JM2 using XMOD JTAG adapter TE0790 adapter.

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titleJTAG Pins ConnectionSMD Coaxial Connectors

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Designator Schematic
JTAG Signal
B2B ConnectorNotes
TMSJ2- 126TDIJ2- 122TDOJ2- 124TCKJ2- 120

There is a DIP switch on TE0790 adapter which must be set accordingly.

J6B230_TX3_PJ1
J9B230_RX3_NJ1
J10B230_RX3_PJ1
J11B230_TX3_PJ1
J12B505_TX0_NJ2
J13B5050TX0_PJ2
J14B505_RX0_NJ2
J15B505_RX0_PJ2


XMOD JTAG

JTAG access to the TEBT080X  is available through B2B connector JB2 using XMOD adapter TE0790.

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titleJTAG Pins Connection

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title Xmod Adapter DIP-Switch Setting Description

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DIP SwitchONOFFDefaultDescription
1Normal modeAdapter board CPLD update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFMust be always in OFF state.
3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)

JTAG Signal

B2B Connector

Notes
TMSJ2- 126
TDIJ2- 122
TDOJ2- 124
TCKJ2- 120


The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) on TE0790 The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switches 3 and 4:switch S2 which must be set as following. 

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title Xmod Adapter DIP-Switch Setting Description

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DIP Switch-3DIP Switch-43.3V (VCC) Pin 5VIO Pin 6Description
OFFOFF3.3V from base (input**)VIO from base (input**)3.3V (pin 5) and VIO (pin 6) sourced from base
OFFON3.3V from USB* (output**)VIO from base (input**)VIO sourced from base by Pin 6
ONOFF3.3V from base (input**)3.3V from base (input**)VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V)
ONON3.3V from USB* (output**)3.3V from USB* (output**)

3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V)

PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JM3.

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anchorTable_SIP_JTG
titlePJTAG Pins Connection
,S2DefaultDescription
1ONUpdate Mode JTAG access to SC CPLD only
2OFFMust be always in OFF state.
3OFFVIO is supplied from Module
4OFF3.3V is supplied by the carrier TEBT0808


PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JB3

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JTAG Signal

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B2B Connector

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I2C Pin header

I2C signals can be accessed through pin header J5.

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titleI2C ConnectionsPJTAG Pins Connection

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Signals

JTAG Signal

B2B Connector

Pin Header NotesPLL_SCLJ2- 90J5- 3PLL_SDAJ2- 92J5- 7

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Notes
PJTAG_TMSJ3- 94
PJTAG_TDIJ3- 90
PJTAG_TDOJ3- 92
PJTAG_TCKJ3- 88
PJTAG_SRSTJ2- 96Connected to SRST_B


Pin header

The I2C signals can be accessed through pin header J5.

J2-72
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titleSMA I2C Connections

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Signals

B2B Connector

Pin HeaderNotes
PLL_SCLJ2- 90J5- 3
PLL_SDAJ2- 92J5- 7

Designator

Signals

B2B Connector

Notes
J6B230_TX3_PJ1-2J9B230_RX3_NJ1-5J10B230_RX3_PJ1-3J11B230_TX3_NJ1-4J12B505_TX0_NJ2-67J13B505_TX0_PJ2-69J14B505_RX0_NJ2-70J15B505_RX0_P


Test Points

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titleTest Points Information

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Test Point

Signals

B2B Connector

Notes
TP 1DDR_1V2J2-135
TP 2PG_PSGTJ2-82
TP 3ERR_STATUSJ2-86
TP 4PLL_FDECJ2-94
TP 5EN_LPDJ2-108
TP 6EN_DDRJ2-112
TP 7PG_PLJ2-104
TP 8PG_PLL_1V8J2-80
TP 9N_PSGTJ2-84
TP 10ERR_OUTJ2-88
TP 11EN_FPDJ2-102
TP 12LP_GOODJ2-106
TP 13PG_FPDJ2-110
TP 14PG_DDRJ2-114
TP 15EN_PLL_PWRJ2-77
TP 16PLL_FINCJ2-81
TP 17PG_GT_RJ2-91
TP 18EN_GT_RJ2-95
TP 19EN_PLJ2-101
TP 20EN_GT_LJ2-79
TP 21PLL_SEL0J2-93
TP 22PG_GT_LJ2-97
TP 23INIT_BJ2-98
TP 24IN1_PJ2-4
TP 25PLL_SEL1J2-87
TP 26PLL_LOLNJ2-85
TP 27PLL_RSTJ2-89
TP 28DX_PJ2-119
TP 29DX_NJ2-121
TP 30IN1_NJ2-6
TP 31B505_CLK0_PJ2-10
TP 32B505_CLK0_NJ2-12
TP 33B505_CLK1_PJ2-16
TP 34B505_CLK1_NJ2-18
TP 35B128_CLK1_PJ2-22
TP 36B128_CLK1_NJ2-24
TP 37CLK0_NJ2-1
TP 38CLK0_PJ2-3
TP 39CLK8_PJ2-7
TP 40CLK8_NJ2-9
TP 41CLK7_PJ2-13
TP 42CLK7_NJ2-15
TP 43IN2_PJ3-66
TP 44IN2_NJ3-68
TP 45B230_CLK1_NJ3-59
TP 46B230_CLK1_PJ3-61
TP 47B229_CLK0_NJ3-65
TP 48B229_CLK0_PJ3-67
TP 49PLL_3V3J3-152
TP 50GNDJ3-155
TP 51PL_1V8J1-121
TP 52PS_1V8J3-147
TP 53SI_PLL_1V8J3-151
TP 54PROG_BJ2-100
TP 55...56GND-


On-board Peripherals

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titleOn Board Peripherals

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Chip/InterfaceDesignatorNotes
DIP SwitchS1...3
LEDsD2...4Red LEDs
OscillatorU2125.00 MHz


DIP Switch

There are thre three DIP Switches, S1, S2, S3.

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titleDIP Switch S1

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DIP Switch S1Signals

B2B

S1 switch
Notes
Notes
S1AMODE0J2-109
S1A

S1BMODE1J2-107
S1B

S1CMODE2J2-105
S1C

S1DMODE3J2-103
S1D


Control signals must be set using DIP Switch S2, S3.

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titleDIP Switch S2

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DIP Switch S2SignalsB2BS2 switchNotesNotes
S2AEN_PSGTJ2-84Position OFF enables power rail
S2BS2AEN_GT_RJ2-95Position OFF enables power rail
S2CS2BEN_GT_LJ2-97Position OFF enables power rail
S2DS2CEN_PLL_PWRJ2-77S2DPosition OFF enables power rail, connected to PG_PL



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titleDIP Switch S3

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DIP Switch S3SignalsB2BS3 switchNotes
S3AEN_DDRJ2-112S3APosition OFF enables power rail
S3BEN_LPDJ2-108S3BPosition OFF enables power rail
S3CEN_PLJ2-101S3CPosition OFF enables power rail
S3DEN_FPDJ2-102S3DPosition OFF enables power rail


LEDs

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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D2RedDONE
Low
Active HighNon User LED
D3RedERR_STATUS
Low
Active HighNon User LED
D4RedERR_OUT
Low
Active HighNon User LED


Clock Sources

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titleOsillators

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DesignatorDescriptionFrequencyNote
U2MEMS Oscillator125.00 MHz


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titlePower Consumption

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Power Input PinTypical Current
VIN3.3VTBD*


* TBD - To Be Determined

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Input oower sourced directly the module, Only one Diode D1 is used for protection.

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titlePower Distribution

Diode D1 is used for inverse polarity protection.

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Power Rails

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titleModule power rails.Power Distribution


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orientation

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portrait

border

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false

ASC

viewerToolbar

repeatTableHeaders

true

default

fitWindow

style

false

widths

diagramDisplayName

sortByColumn1
sortEnabledfalse
cellHighlightingtrue

lboxtrue
revision4
diagramNameTEBT0808_PWR_PD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth640


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Power Rails

1.8V for PL Banks
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Power Rail Name

B2B J1 PinsB2B J2 PinsB2B J3 Pins

Directions

Note
PL_DCIN151, 153, 155, 157, 159--Output-
DCDCIN

-

154, 156, 158, 160,
153, 155, 157, 159

-Output-
LP_DCDC-138, 140, 142, 144-Output-
PS_BATT-125-Output-
GT_DCDC--157, 158, 159, 160Output-
PLL_3V3--152Output-
Power Rail Name

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

B2B

JM4 Pin

DirectionNotes
3.3V151,153,155,157,159140,142,144,154,156,158,160,
153,155,157,159		157,158,159,160-OutputCarrier power supply to module power rails PL_DCDCIN. DCDCIN, LP_DCDC, GT_DCDC, PL_3V3V

VCCO_47

--43, 44-OutputConnected to 1.8 (SI_PLL_1V8)
VCCO_48--15,16-OutputConnected to 1.8 (SI_PLL_1V8)
VCCO_64---58, 106OutputConnected to 1.8 (PL_1V8)
VCCO_65---69, 105OutputConnected to 1.8 (PL_1V8)
VCCO_6690,120---OutputConnected to 1.8 (PL_1V8)
PS_1V8-99,147, 148-Input
PLL_3V3--152-Output3.3V
PL_1_V8121,121---Input
SI_PLL_1V8--151Input-
InputDDR 1V2-135--Inout
PS_1V8-99147, 148Input-
PL_1V891, 121
PL_3V3
--
152
Input-
OutputConnected to 3.3VPSBAT
DDR_1V2-135-
125
Input-
-Output1.2V..1.5V, abs. max 2V