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The Trenz Electronic TEBT0808 is a test fixture for module TE0808(REV01REV02, REV02REV03) and TE0803(REV01) series.
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- Modules
- On Board
- Done/Error/Status LEDs
- MEMS Oscillator 125.00 MHz
- Boot Mode DIP-Switch
- 2x DIP-Switches to control TE080x power domains
- Interface
- Pin Header for TE0790 JTAG/UART Adapter
- ARM JTAG header
10 - Done/Error/Status LEDs
- Board to Board (B2B) Connectors
- One PL GT with 4x SMA Connectors
- One PS GT with 4x SMA Connectors
- MEMS Oscillator 125.0 MHz
- Boot Mode DIP-Switch
- 2x DIP-Switches to control TE080x power domains
- One pre-assembled TE0790 XMOD FTDI JTAG adapter
- Power:
- 3.3 V (Nominal Supply Voltage
Power Supply:- Single 3.3V (Direct modules power supply)
- Dimension: 90mm x 90mmOthers:
- One pre-assembled TE0790 XMOD FTDI JTAG adapter
Block Diagram
| Page properties |
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add drawIO object here.
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEBT0808 Block Diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 1823 |
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| diagramName | TEBT0808_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 640636 |
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| Scroll Only |
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 Image Modified
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Main Components
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEBT0808 Main Components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 4 |
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| diagramName | TEBT0808_OV_MC |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 640 |
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| Scroll Only |
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 Image Modified
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- Uninsulated Power Jack. J7-J8
- SMA Coaxial straight. J6- J9...15
- Surface Mount Schottky Barrier Rectifier. D1
- ARM PJTAG Pin Header J16
- I2C Pin Header, J5
- Board to Board Connectors. J1...4
- MEMS Oscillator, U2
- On-Board LEDs, D2...4
- DIP-Switch, S1...3
- XMOD JTAG Baseheader, JX1
Initial Delivery State
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| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot Process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| M3 | M2 | M1 | M0 | Bootmode Hex | Bootmode | Notes |
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| ON | ON | ON | ON | 0xF0b0000 | PS Main JTAG (TE0790 USB JTAG) | DIPs are inverted | | ON | ON | OFF | ON | 0xD0b0010 | SPI Flash (dual parallel, 4bit x 2, 32bit Addressing) | ONDIPs are inverted | | OFFOFF | ON | ON | OFFON | 0x80b1000 | PJTAG(MIO29:26) | DIPs are inverted |
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset Process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | B2B | Note |
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PLL_RST | J2-89 |
| | SRST_B | J2-96 | Connected to PJTAG0_SRST - J16 |
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Board to Board (B2B) I/Os
FPGA bank number and number TEBT0808 has four B2B Connectors and each connector has 160 pins. Number of I/O signals and Interfaces connected to the B2B connector:connectors is as following table:
| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| B2B Connector | Interfaces | Number of I/O | Notes |
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J1
| User I/O | 22 46 Single Ended, 11 23 Differential 8 16 Single Ended, 4 8 Differential8 16 Single Ended, 4 8 Differential8 16 Single Ended, 4 8 Differential 3 4 Single Ended | IOs are Loop-Back IOs are Loop-Back IOs are Loop-Back IOs are Loop-Back Connected to Module FPGA, Bank 66 Connected to Module FPGA, Bank 228 Connected to Module FPGA, Bank 229 Connected to Module FPGA, Bank 230 VCCO_66, PL_1V8 | J2
| Ethernet PHY User IO | 32 28 Single Ended, 16 14 Differential 4 6 Single Ended, 16 Differential Connected to Module FPGA, Bank 505 Connected to Module FPGA, Bank 1283 Differential | IOs are Loop-Back IOs are Loop-Back | | Boot Mode | 4 Single Ended | MODE0...3 | | Control Signals | 15 25 Single Ended | PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE | Power Control Signal | 10 Single Ended | , EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L | | JTAG Interface | 7 Single Ended | TCK, TDI, TMS, TDO, MR, Rxd, Txd | | WANNE2I2C | 2 Single Ended | PLL_SCL, PLL_SDA | | Clock | 6 Single Ended, 3 Differential | CLK0, CLK7, CLK8 | J3
| User I/OIO | 12 24 Single Ended, 6 12 Differential 12 24 Single Ended, 6 12 Differential | Connected to Module FPGA, Bank 48 Connected to Module FPGA, Bank 47 | | Clock | 6 Single Ended, 3 Differential | CLK228, CLK229, CLK230 | | PJTAG Interface | 7 4 Single Ended | PJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO, | | MIO | 27 45 Single Ended | MIO19MIO13..7677 | | UART | 2 Single Ended | TXD, RXD | | Power pinsControl Signals | 4 Single Ended | PS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3 | | J4 | User I/O | 48 Single Ended, 62 Differential 24 Differential 48 Single Ended, 24 Differential 4 Single Ended 4 Single Ended | IOs are Loop-Back IOs are Loop-Back B64_T0...3 B65_T0...3 Connected to Module FPGA, Bank 64 Connected to Module FPGA, Bank 64 | | Power pins | 4 Single Ended | VCCO_64, VCCO65 |
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SMA Coaxial Connectors
TEBT0808 is equipped with 8 SMD Coaxial Connectors. JTAG access to the TEBT080X is available through B2B connector JB2 using XMOD JTAG adapter TE0790 adapter.
| Scroll Title |
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| anchor | Table_SIP_JTGSMDCoax |
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| title | JTAG Pins ConnectionSMD Coaxial Connectors |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal| TMS | J2- 126 | TDI | J2- 122 | TDO | J2- 124 | TCK | J2- 120 | |
There is a DIP switch, S2, on TE0790 adapter which must be set accordingly.
| J6 | B230_TX3_P | J1 |
| | J9 | B230_RX3_N | J1 |
| | J10 | B230_RX3_P | J1 |
| | J11 | B230_TX3_P | J1 | | J12 | B505_TX0_N | J2 |
| | J13 | B5050TX0_P | J2 |
| | J14 | B505_RX0_N | J2 |
| | J15 | B505_RX0_P | J2 |
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XMOD JTAG
JTAG access to the TEBT080X is available through B2B connector JB2 using XMOD adapter TE0790.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG Pins Connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector | Notes |
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| TMS | J2- 126 |
| | TDI | J2- 122 |
| | TDO | J2- 124 |
| | TCK | J2- 120 |
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| Scroll Title |
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| anchor | Table_SIP_Xmod_DIP |
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| title | Xmod Adapter DIP-Switch Setting Description |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| DIP Switch | ON | OFF | Default | Description |
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| 1 | Normal mode | Adapter board CPLD update mode | ON | Update Mode JTAG access to SC CPLD only |
| 2 | Do not use (illegal setting) | Normal mode | OFF | Must be always in OFF state. |
| 3 | VIO connected to 3.3V | Power VIO from pin header J2 | OFF | User I/O Voltage |
4 | Power 3.3V from USB | Power 3.3V from pin header J2 | OFF | Power on-board peripherals (FTDI chip & SC CPLD, ...)
The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) on TE0790 can be configured by the DIP-switch S2 -3 and S2-4 on TE0790:which must be set as following.
| Scroll Title |
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| anchor | Table_SIP_Xmod_DIP |
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| title | Xmod Adapter DIP-Switch Setting Description |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| DIP Switch-3 | DIP Switch-4 | 3.3V (VCC) Pin 5 | VIO Pin 6 | Description |
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| OFF | OFF | 3.3V from base | VIO from base | 3.3V (pin 5) and VIO (pin 6) sourced from base | | OFF | ON | 3.3V from USB | VIO from base | VIO sourced from base by Pin 6 | | ,S2 | Default | Description |
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| 1 | ON | Update Mode JTAG access to SC CPLD only | | 2 | OFF | Must be always in OFF state. | | 3 | OFF | VIO is supplied from Module | | 4ON | OFF | 3.3V from base | 3.3V from base | VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V) | | ON | ON | 3.3V from USB | 3.3V from USB | 3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V) |
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PJTAG
PJTAG access to the TEBT0808 is available through B2B connector JB3.
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| anchor | Table_SIP_JTG |
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| title | PJTAG Pins Connection |
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| is supplied by the carrier TEBT0808 |
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PJTAG
PJTAG access to the TEBT0808 is available through B2B connector JB3
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JTAG Signal
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B2B Connector
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I2C signals can be accessed through pin header J5.
| Scroll Title |
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| anchor | Table_SIP_I2CJTG |
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| title | I2C ConnectionsPJTAG Pins Connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signals| Pin Header | Notes | PLL_SCL | J2- 90 | J5- 3 | PLL_SDA | J2- 92 | J5- 7 | |
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| Notes |
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| PJTAG_TMS | J3- 94 |
| | PJTAG_TDI | J3- 90 |
| | PJTAG_TDO | J3- 92 |
| | PJTAG_TCK | J3- 88 |
| | PJTAG_SRST | J2- 96 | Connected to SRST_B |
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The I2C signals can be accessed through pin header J5.
| Scroll Title |
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| anchor | Table_SIP_SMAI2C |
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| title | SMA I2C Connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Designator | Notes | J6 | B230_TX3_P | J1-2 | J9 | B230_RX3_N | J1-5 | | Pin Header | Notes |
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| PLL_SCL | J2- 90 | J5- 3 |
| | PLL_SDA | J2- 92 | J5- 7 |
J10 | B230_RX3_P | J1-3 | J11 | B230_TX3_N | J1-4 | J12 | B505_TX0_N | J2-67 | J13 | B505_TX0_P | J2-69 | J14 | B505_RX0_N | J2-70 | J15 | B505_RX0_P | J2-72
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Test Points
| Scroll Title |
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| anchor | Table_SIP_TestPoint |
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| title | Test Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Test Point | Signals | B2B Connector | Notes |
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| TP 1 | DDR_1V2 | J2-135 |
| | TP 2 | PG_PSGT | J2-82 |
| | TP 3 | ERR_STATUS | J2-86 |
| | TP 4 | PLL_FDEC | J2-94 |
| | TP 5 | EN_LPD | J2-108 |
| | TP 6 | EN_DDR | J2-112 |
| | TP 7 | PG_PL | J2-104 |
| | TP 8 | PG_PLL_1V8 | J2-80 |
| | TP 9 | N_PSGT | J2-84 |
| | TP 10 | ERR_OUT | J2-88 |
| | TP 11 | EN_FPD | J2-102 |
| | TP 12 | LP_GOOD | J2-106 |
| | TP 13 | PG_FPD | J2-110 |
| | TP 14 | PG_DDR | J2-114 |
| | TP 15 | EN_PLL_PWR | J2-77 |
| | TP 16 | PLL_FINC | J2-81 |
| | TP 17 | PG_GT_R | J2-91 |
| | TP 18 | EN_GT_R | J2-95 |
| | TP 19 | EN_PL | J2-101 |
| | TP 20 | EN_GT_L | J2-79 |
| | TP 21 | PLL_SEL0 | J2-93 |
| | TP 22 | PG_GT_L | J2-97 |
| | TP 23 | INIT_B | J2-98 |
| | TP 24 | IN1_P | J2-4 |
| | TP 25 | PLL_SEL1 | J2-87 |
| | TP 26 | PLL_LOLN | J2-85 |
| | TP 27 | PLL_RST | J2-89 |
| | TP 28 | DX_P | J2-119 |
| | TP 29 | DX_N | J2-121 |
| | TP 30 | IN1_N | J2-6 |
| | TP 31 | B505_CLK0_P | J2-10 |
| | TP 32 | B505_CLK0_N | J2-12 |
| | TP 33 | B505_CLK1_P | J2-16 |
| | TP 34 | B505_CLK1_N | J2-18 |
| | TP 35 | B128_CLK1_P | J2-22 |
| | TP 36 | B128_CLK1_N | J2-24 |
| | TP 37 | CLK0_N | J2-1 |
| | TP 38 | CLK0_P | J2-3 |
| | TP 39 | CLK8_P | J2-7 |
| | TP 40 | CLK8_N | J2-9 |
| | TP 41 | CLK7_P | J2-13 |
| | TP 42 | CLK7_N | J2-15 |
| | TP 43 | IN2_P | J3-66 |
| | TP 44 | IN2_N | J3-68 |
| | TP 45 | B230_CLK1_N | J3-59 |
| | TP 46 | B230_CLK1_P | J3-61 |
| | TP 47 | B229_CLK0_N | J3-65 |
| | TP 48 | B229_CLK0_P | J3-67 |
| | TP 49 | PLL_3V3 | J3-152 |
| | TP 50 | GND | J3-155 |
| | TP 51 | PL_1V8 | J1-121 |
| | TP 52 | PS_1V8 | J3-147 |
| | TP 53 | SI_PLL_1V8 | J3-151 |
| | TP 54 | PROG_B | J2-100 |
| | TP 55...56 | GND | - |
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On-board Peripherals
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On Board Peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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DIP Switch
There are thre three DIP Switches, S1, S2, S3.
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| Scroll Title |
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| anchor | Table_OBP_DIP |
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| title | DIP Switch S1 |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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S1 switchNotesS1AS1BS1C| S1D |
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Control signals must be set using DIP Switch S2, S3.
| Scroll Title |
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| anchor | Table_OBP_DIP |
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| title | DIP Switch S2 |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| DIP Switch S2 | Signals | B2B | S2 switchNotesNotes |
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| S2A | EN_PSGT | J2-84 | Position OFF enables power rail | | S2BS2A | EN_GT_R | J2-95 | Position OFF enables power rail | | S2CS2B | EN_GT_L | J2-97 | Position OFF enables power rail | | S2DS2C | EN_PLL_PWR | J2-77 | S2D | Position OFF enables power rail, connected to PG_PL |
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| Scroll Title |
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| anchor | Table_OBP_DIP |
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| title | DIP Switch S3 |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| DIP Switch S3 | Signals | B2B | S3 switch | Notes |
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| S3A | EN_DDR | J2-112 | S3A | Position OFF enables power rail | | S3B | EN_LPD | J2-108108 | S3B | Position OFF enables power rail | | S3CS3B | EN_PL | J2-101 | S3C | Position OFF enables power rail | | S3D | EN_FPD | J2-102 | S3D | Position OFF enables power rail |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Connected to | Active Level | Note |
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| D2 | Red | DONE | Active High | Non User LED | | D3 | Red | ERR_STATUS | Active High | Non User LED | | D4 | Red | ERR_OUT | Active High | Non User LED |
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| Scroll Title |
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
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| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Power Input Pin | Typical Current |
|---|
| VIN3.3V | TBD* |
|
* TBD - To Be Determined
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Input oower sourced directly the module, Only one Diode D1 is used for inverse polarity protection.
| Scroll Title |
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 4 |
|---|
| diagramName | TEBT0808_PWR_PD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 640 |
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|
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| Scroll Only |
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| Page properties |
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
| Include Page |
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| PD:6 x 6 SoM LSHM B2B ConnectorsPD: |
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| 6 x 6 SoM LSHM B2B Connectors |
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| Include Page |
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| PD:5.2 x 7.6 SoM UltraSoM+ ST5 and SS5 B2B ConnectorsPD: |
|---|
| 5.2 x 7.6 SoM UltraSoM+ ST5 and SS5 B2B Connectors |
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|
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| Scroll Title |
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| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
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| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
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| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | | 2020-05-11 | v.54 | John Hartfiel | add notes to DIP section - Correction on configuration signal section
| | 2020-01-24 | v.49 | Pedram Babakhani | | -- | all | Edit | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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Disclaimer
| Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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