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changes.mady.by.user Pedram Babakhani

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changes.mady.by.user Vadim Yunitski

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  • Modules
    • TE0808, TE0803
  • On Board
    • Done/Error/Status LEDs
    • MEMS Oscillator 125.00 MHz
    • Boot Mode DIP-Switch
    • 2x DIP-Switches to control TE080x power domains
  • Interface
    • Pin Header for TE0790 JTAG/UART Adapter
    • ARM JTAG header
    • Pin Header for I2C
    • Board to Board (B2B) Connectors
    • One PL GT with 4x SMA Connectors
    • One PS GT with 4x SMA Connectors
    • One pre-assembled TE0790 XMOD FTDI JTAG adapter
  • Power:
    • 3.3 V (Nominal Supply Voltage)
  • Dimension: 90mm x 90mm

Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_OV_BD
titleTEBT0808 Block Diagram


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borderfalse
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Main Components

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  1. Uninsulated Power Jack. J7-J8
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. ARM PJTAG Pin Header J16
  5. I2C Pin Header, J5
  6. Board to Board Connectors. J1...4
  7. MEMS Oscillator, U2
  8. On-Board LEDs, D2...4
  9. DIP-Switch, S1...3
  10. XMOD JTAG Baseheader, JX1

Initial Delivery State

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Scroll Title
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titleBoot Process.

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ON
M3M2M1M0Bootmode HexBootmodeNotes
ONONONON0xF0b0000PS Main JTAG (TE0790 USB JTAG)DIPs are inverted
ONONOFFON0xD0b0010SPI Flash (dual parallel, 4bit x 2, 32bit Addressing)DIPs are inverted
OFFONOFFONOFFON0x80b1000PJTAG(MIO29:26)DIPs are inverted



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titleReset Process.

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Signal

B2BNote

PLL_RST

J2-89
SRST_BJ2-96Connected to PJTAG0_SRST - J16


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TEBT0808 has four B2B Connectors and each connector has 160 pins. FPGA bank number and number Number of I/O signals and Interfaces connected to the B2B connectorconnectors is as following table:

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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O

46 Single Ended, 23 Differential

16 Single Ended, 8 Differential

16 Single Ended, 8 Differential

16 Single Ended, 8 Differential

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

PL_1V8

J2

User IO

28 Single Ended, 14 Differential

6 Single Ended, 3 Differential

IOs are Loop-Back

IOs are Loop-Back

Boot Mode 4 Single EndedMODE0...3
Control Signals25 Single Ended

PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE, EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L

JTAG Interface7 Single EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
I2C 2 Single EndedPLL_SCL, PLL_SDA
Clock

6 Single Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User IO

24 Single Ended, 12 Differential

24 Single Ended, 12 Differential

Connected to Module FPGA, Bank 48

Connected to Module FPGA, Bank 47

Clock6 Single Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface7 4 Single EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO45 Single EndedMIO13..77
UART2 Single EndedTXD, RXD
Power Control Signals4 Single EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3
J4User I/O

48 Single Ended, 24 Differential

48 Single Ended, 24 Differential

4 Single Ended

4 Single Ended

IOs are Loopare Loop-Back

IOs are Loopare Loop-Back

B64_T0...3

B65_T0...3

Power pins4 Single EndedVCCO_64, VCCO65

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SMA Coaxial Connectors

TEBT0808 is equipped with 8 SMD Coaxial Connectors. 

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JTAG access to the TEBT080X  is available through B2B connector JB2 using XMOD JTAG adapter TE0790 adapter.

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titleJTAG Pins Connection

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JTAG Signal

B2B Connector

Notes
TMSJ2- 126
TDIJ2- 122
TDOJ2- 124
TCKJ2- 120

There is a DIP switch, S2, on TE0790 adapter which must be set accordingly.



The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) on TE0790 can be configured by the DIP-switch S2 which must be set as following. 

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anchorTable_SIP_Xmod_DIP
title Xmod Adapter DIP-Switch Setting Description

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DIP SwitchON,S2OFFDefaultDescription
1Normal modeAdapter board CPLD update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFMust be always in OFF state.
3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)

The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switch S2-3 and S2-4 on TE0790:

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anchorTable_SIP_Xmod_DIP
title Xmod Adapter DIP-Switch Setting Description

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3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V)

OFFVIO is supplied from Module
4OFF3.3V is supplied by the carrier TEBT0808


PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JB3

PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JB3.

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anchorTable_SIP_JTG
titlePJTAG Pins Connection

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JTAG Signal

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B2B Connector

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Pin header

I2C signals can be accessed through pin header J5.

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titleI2C ConnectionsPJTAG Pins Connection

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Signals

JTAG Signal

B2B Connector

Pin Header NotesPLL_SCLJ2- 90J5- 3PLL_SDAJ2- 92J5- 7

SMA Coaxial

Notes
PJTAG_TMSJ3- 94
PJTAG_TDIJ3- 90
PJTAG_TDOJ3- 92
PJTAG_TCKJ3- 88
PJTAG_SRSTJ2- 96Connected to SRST_B


Pin header

The I2C signals can be accessed through pin header J5.

J2-72
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titleSMA I2C Connections

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Signals

B2B Connector

Pin HeaderNotes
PLL_SCLJ2- 90J5- 3
PLL_SDAJ2- 92J5- 7

Designator

Signals

B2B Connector

Notes
J6B230_TX3_PJ1-2J9B230_RX3_NJ1-5J10B230_RX3_PJ1-3J11B230_TX3_NJ1-4J12B505_TX0_NJ2-67J13B505_TX0_PJ2-69J14B505_RX0_NJ2-70J15B505_RX0_P


Test Points

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titleTest Points Information

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Test Point

Signals

B2B Connector

Notes
TP 1DDR_1V2J2-135
TP 2PG_PSGTJ2-82
TP 3ERR_STATUSJ2-86
TP 4PLL_FDECJ2-94
TP 5EN_LPDJ2-108
TP 6EN_DDRJ2-112
TP 7PG_PLJ2-104
TP 8PG_PLL_1V8J2-80
TP 9N_PSGTJ2-84
TP 10ERR_OUTJ2-88
TP 11EN_FPDJ2-102
TP 12LP_GOODJ2-106
TP 13PG_FPDJ2-110
TP 14PG_DDRJ2-114
TP 15EN_PLL_PWRJ2-77
TP 16PLL_FINCJ2-81
TP 17PG_GT_RJ2-91
TP 18EN_GT_RJ2-95
TP 19EN_PLJ2-101
TP 20EN_GT_LJ2-79
TP 21PLL_SEL0J2-93
TP 22PG_GT_LJ2-97
TP 23INIT_BJ2-98
TP 24IN1_PJ2-4
TP 25PLL_SEL1J2-87
TP 26PLL_LOLNJ2-85
TP 27PLL_RSTJ2-89
TP 28DX_PJ2-119
TP 29DX_NJ2-121
TP 30IN1_NJ2-6
TP 31B505_CLK0_PJ2-10
TP 32B505_CLK0_NJ2-12
TP 33B505_CLK1_PJ2-16
TP 34B505_CLK1_NJ2-18
TP 35B128_CLK1_PJ2-22
TP 36B128_CLK1_NJ2-24
TP 37CLK0_NJ2-1
TP 38CLK0_PJ2-3
TP 39CLK8_PJ2-7
TP 40CLK8_NJ2-9
TP 41CLK7_PJ2-13
TP 42CLK7_NJ2-15
TP 43IN2_PJ3-66
TP 44IN2_NJ3-68
TP 45B230_CLK1_NJ3-59
TP 46B230_CLK1_PJ3-61
TP 47B229_CLK0_NJ3-65
TP 48B229_CLK0_PJ3-67
TP 49PLL_3V3J3-152
TP 50GNDJ3-155
TP 51PL_1V8J1-121
TP 52PS_1V8J3-147
TP 53SI_PLL_1V8J3-151
TP 54PROG_BJ2-100
TP 55...56GND-


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Scroll Title
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titleOn Board Peripherals

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Chip/InterfaceDesignatorNotes
DIP SwitchS1...3
LEDsD2...4Red LEDs
OscillatorU2125.00 MHz


DIP Switch

There are thre three DIP Switches, S1, S2, S3.

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Scroll Title
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titleDIP Switch S1

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DIP Switch S1Signals

B2B

S1 switch
Notes
Notes
S1AMODE0J2-109
S1A

S1BMODE1J2-107
S1B

S1CMODE2J2-105
S1C

S1DMODE3J2-103
S1D


Control signals must be set using DIP Switch S2, S3.

Scroll Title
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titleDIP Switch S2

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DIP Switch S2SignalsB2BS2 switchNotesNotes
S2AEN_PSGTJ2-84Position OFF enables power rail
S2BS2AEN_GT_RJ2-95Position OFF enables power rail
S2CS2BEN_GT_LJ2-97Position OFF enables power rail
S2DS2CEN_PLL_PWRJ2-77S2DPosition OFF enables power rail, connected to PG_PL



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titleDIP Switch S3

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DIP Switch S3SignalsB2BS3 switchNotes
S3AEN_DDRJ2-112S3APosition OFF enables power rail
S3BEN_LPDJ2-108J2-108S3BPosition OFF enables power rail
S3CS3BEN_PLJ2-101S3CPosition OFF enables power rail
S3DEN_FPDJ2-102S3DPosition OFF enables power rail


LEDs

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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D2RedDONEActive HighNon User LED
D3RedERR_STATUSActive HighNon User LED
D4RedERR_OUTActive HighNon User LED


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titlePower Consumption

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Power Input PinTypical Current
VIN3.3VTBD*


* TBD - To Be Determined

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  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

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    PD:6 x 6 SoM LSHM B2B ConnectorsPD:
    6 x 6 SoM LSHM B2B Connectors

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PD:5.2 x 7.6 SoM UltraSoM+ ST5 and SS5 B2B ConnectorsPD:
5.2 x 7.6 SoM UltraSoM+ ST5 and SS5 B2B Connectors

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titleDocument change history.

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DateRevisionContributorDescription

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  • Updated block diagram
2020-05-11v.54John Hartfiel

  • add notes to DIP section

  • Correction on configuration signal section
2020-01-24v.49Pedram Babakhani
  • Initial Release

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Disclaimer

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