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anchor	Figure_OV_BD
title	TEBT0808 Block Diagram

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Main Components

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title	Boot Process.

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ON

M3	M2	M1	M0	Bootmode Hex	Bootmode	Notes
ON	ON	ON	ON	0xF0b0000	PS Main JTAG (TE0790 USB JTAG)	DIPs are inverted
ON	ON	OFF	ON	0xD0b0010	SPI Flash (dual parallel, 4bit x 2, 32bit Addressing)	DIPs are inverted
OFFOFF	ON	ON	OFFON	0x80b1000	PJTAG(MIO29:26)	DIPs are inverted

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title	Reset Process.

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Signal	B2B	Note
PLL_RST	J2-89
SRST_B	J2-96	Connected to PJTAG0_SRST - J16

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TEBT0808 has four B2B Connectors and each connector has 160 pins. FPGA bank number and number Number of I/O signals and Interfaces connected to the B2B connectorconnectors is as following table:

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title	General PL I/O to B2B connectors information

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B2B Connector	Interfaces	Number of I/O	Notes
J1	User I/O	46 Single Ended, 23 Differential 16 Single Ended, 8 Differential 16 Single Ended, 8 Differential 16 Single Ended, 8 Differential 4 Single Ended	IOs are Loop-Back IOs are Loop-Back IOs are Loop-Back IOs are Loop-Back PL_1V8
J2	User IO	28 Single Ended, 14 Differential 6 Single Ended, 3 Differential	IOs are Loop-Back IOs are Loop-Back
	Boot Mode	4 Single Ended	MODE0...3
	Control Signals	25 Single Ended	PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE, EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L
	JTAG Interface	7 Single Ended	TCK, TDI, TMS, TDO, MR, Rxd, Txd
	I²C	2 Single Ended	PLL_SCL, PLL_SDA
	Clock	6 Single Ended, 3 Differential	CLK0, CLK7, CLK8
J3	User IO	24 Single Ended, 12 Differential 24 Single Ended, 12 Differential	Connected to Module FPGA, Bank 48 Connected to Module FPGA, Bank 47
	Clock	6 Single Ended, 3 Differential	CLK228, CLK229, CLK230
	PJTAG Interface	4 Single Ended	PJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
	MIO	45 Single Ended	MIO13..77
	UART	2 Single Ended	TXD, RXD
	Power Control Signals	4 Single Ended	PS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3
J4	User I/O	48 Single Ended, 24 Differential 48 Single Ended, 24 Differential 4 Single Ended 4 Single Ended	IOs are Loop-Back IOs are Loop-Back B64_T0...3 B65_T0...3
J4	Power pins	4 Single Ended	VCCO_64, VCCO65

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title	DIP Switch S2

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DIP Switch S2	Signals	B2B	Notes
S2A	EN_PSGT	J2-84	Position OFF enables power rail
S2B	EN_GT_R	J2-95	Position OFF enables power rail
S2C	EN_GT_L	J2-97	Position OFF enables power rail
S2D	EN_PLL_PWR	J2-77	Position OFF enables power rail, connected to PG_PL

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DIP Switch S3	Signals	B2B	S3 switch	Notes
S3A	EN_DDR	J2-112	S3A	Position OFF enables power rail
S3B	EN_LPD	J2-108	S3B	Position OFF enables power rail
S3C	EN_PL	J2-101	S3C	Position OFF enables power rail
S3D	EN_FPD	J2-102	S3D	Position OFF enables power rail

LEDs

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Designator	Color	Connected to	Active Level	Note
D2	Red	DONE	Active High	Non User LED
D3	Red	ERR_STATUS	Active High	Non User LED
D4	Red	ERR_OUT	Active High	Non User LED

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id	Comments

This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
PD:6 x 6 SoM LSHM B2B ConnectorsPD:
6 x 6 SoM LSHM B2B Connectors

Include Page

	PD:5.2 x 7.6 SoM UltraSoM+ ST5 and SS5 B2B ConnectorsPD:
	5.2 x 7.6 SoM UltraSoM+ ST5 and SS5 B2B Connectors

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Date

Revision

Contributor

Description

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infoType	Current version
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Page info

infoType	Modified by
type	Flat
showVersions	false

Updated block diagram

2020-05-11

v.54

John Hartfiel

add notes to DIP section
Correction on configuration signal section

2020-01-24

v.49

Pedram Babakhani

Initial Release

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Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Versions Compared

Old Version 47

New Version Current

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Main Components

LEDs

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