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some sources available on public doc TEBT0808 TRM

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Template Revision 2.5

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

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Note for Download Link of the Scroll ignore macro:


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Download PDF version of this document.


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Table of Contents

Table of Contents

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The Trenz Electronic TEBT0808 -01 is a testboard test fixture for module TE0808(REV 02 and 03) as well as for TE0803 (REV 01)REV02, REV03) and TE0803(REV01) series.

Refer to http://trenz.org/tebt0808-info for the current online version of this manual and other available documentation.

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Modules
    • TE0808, TE0803
  • On Board
    • Done/Error/Status LEDs
    • MEMS Oscillator 125.00 MHz
    • Boot Mode DIP-Switch
    • 2x DIP-Switches to control TE080x power domains
  • Interface
    • Pin
  • Accepts TE0808 / TE0803
  • Single 3.3V input
    • Header for TE0790 JTAG/UART Adapter
    20 Pin
    • ARM JTAG header
    (connected to MIO JTAG 0)
    10
    • Pin
    I2C header for Silabs Clock Builder Field ProgrammerDone, Error/Status LEDs
    • Header for I2C
    • Board to Board (B2B) Connectors
    • One PL GT with 4x SMA
    connectors
    • Connectors
    • One PS GT with
    SMA connectors
  • GT local loopback
  • PL I/O loopbacks
  • PS I/O loopbacks
  • Boot Mode switches
  • Power control switches to control TE0808 power domains
    • 4x SMA Connectors
    • One pre-assembled TE0790 XMOD FTDI JTAG adapter

Supported Bootmodes are SPI and JTAG.

  • Power:
    • 3.3 V (Nominal Supply Voltage)
  • Dimension: 90mm x 90mm

Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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draw.io Diagram
border
true
false
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Main Components

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diagramWidth640
revision3


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  1. Uninsulated 2 mm rigid socket. J8-J7Power Jack. J7-J8
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. ARM PJTAG Pin Header J16
  5. I2C Pin Header, J5Box Headers, Straight/Angled J5-J16
  6. Board to Board ConnectorConnectors. J1...4
  7. Clock MEMS Oscillator, U2
  8. On-Board LEDLEDs, D1D2...34
  9. DIP-Switch, S1...3
  10. XMOD JTAG Baseheader,  JX1

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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Storage device name

Content

Notes

Quad SPI Flash-

EEPROM-DDR3 SDRAMSystem Controller CPLD

-


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

Boot mode can be set by DIP-Switch S1.

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titleBoot processProcess.

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MODE Signal State

Boot Mode
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titleReset process.
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Signal

B2BI/ONote

Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

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M3M2M1M0BootmodeBootmodeNotes
ONONONON0b0000PS Main JTAG (TE0790 USB JTAG)DIPs are inverted
ONONOFFON0b0010SPI Flash (dual parallel, 4bit x 2, 32bit Addressing)DIPs are inverted
OFFONONON0b1000PJTAG(MIO29:26)DIPs are inverted



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titleReset Process.

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Signal

B2BNote

PLL_RST

J2-89
SRST_BJ2-96Connected to PJTAG0_SRST - J16


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

TEBT0808 has four B2B Connectors and each connector has 160 pins. Number of I/O signals and Interfaces connected to the B2B connectors is as following table:

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JTAG access to the TExxxx SoM through B2B connector JMX.

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titleJTAG pins connection

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JTAG Signal

B2B Connector
TMSTDITDOTCKJTAG_EN

MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

InterfacesNumber of I/ONotes
J1

User I/O

46 Single Ended, 23 Differential

16 Single Ended, 8 Differential

16 Single Ended, 8 Differential

16 Single Ended, 8 Differential

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

PL_1V8

J2

User IO

28 Single Ended, 14 Differential

6 Single Ended, 3 Differential

IOs are Loop-Back

IOs are Loop-Back

Boot Mode 4 Single EndedMODE0...3
Control Signals25 Single Ended

PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE, EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L

JTAG Interface7 Single EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
I2C 2 Single EndedPLL_SCL, PLL_SDA
Clock

6 Single Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User IO

24 Single Ended, 12 Differential

24 Single Ended, 12 Differential

Connected to Module FPGA, Bank 48

Connected to Module FPGA, Bank 47

Clock6 Single Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface4 Single EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO45 Single EndedMIO13..77
UART2 Single EndedTXD, RXD
Power Control Signals4 Single EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3
J4User I/O

48 Single Ended, 24 Differential

48 Single Ended, 24 Differential

4 Single Ended

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

B64_T0...3

B65_T0...3

Power pins4 Single EndedVCCO_64, VCCO65


SMA Coaxial Connectors

TEBT0808 is equipped with 8 SMD Coaxial Connectors. 

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Designator SchematicB2B ConnectorNotes
J6B230_TX3_PJ1
J9B230_RX3_NJ1
J10B230_RX3_PJ1
J11B230_TX3_PJ1
J12B505_TX0_NJ2
J13B5050TX0_PJ2
J14B505_RX0_NJ2
J15B505_RX0_PJ2


XMOD JTAG

JTAG access to the TEBT080X  is available through B2B connector JB2 using XMOD adapter TE0790.

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JTAG Signal

B2B Connector

Notes
TMSJ2- 126
TDIJ2- 122
TDOJ2- 124
TCKJ2- 120


The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) on TE0790 can be configured by the DIP-switch S2 which must be set as following. 

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DIP Switch,S2DefaultDescription
1ONUpdate Mode JTAG access to SC CPLD only
2OFFMust be always in OFF state.
3OFFVIO is supplied from Module
4OFF3.3V is supplied by the carrier TEBT0808


PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JB3.

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JTAG Signal

B2B Connector

Notes
PJTAG_TMSJ3- 94
PJTAG_TDIJ3- 90
PJTAG_TDOJ3- 92
PJTAG_TCKJ3- 88
PJTAG_SRSTJ2- 96Connected to SRST_B


Pin header

The I2C signals can be accessed through pin header J5.

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Signals

B2B Connector

Pin HeaderNotes
PLL_SCLJ2- 90J5- 3
PLL_SDAJ2- 92J5- 7


Test Points

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Test Point

Signals

B2B Connector

Notes
TP 1DDR_1V2J2-135
TP 2PG_PSGTJ2-82
TP 3ERR_STATUSJ2-86
TP 4PLL_FDECJ2-94
TP 5EN_LPDJ2-108
TP 6EN_DDRJ2-112
TP 7PG_PLJ2-104
TP 8PG_PLL_1V8J2-80
TP 9N_PSGTJ2-84
TP 10ERR_OUTJ2-88
TP 11EN_FPDJ2-102
TP 12LP_GOODJ2-106
TP 13PG_FPDJ2-110
TP 14PG_DDRJ2-114
TP 15EN_PLL_PWRJ2-77
TP 16PLL_FINCJ2-81
TP 17PG_GT_RJ2-91
TP 18EN_GT_RJ2-95
TP 19EN_PLJ2-101
TP 20EN_GT_LJ2-79
TP 21PLL_SEL0J2-93
TP 22PG_GT_LJ2-97
TP 23INIT_BJ2-98
TP 24IN1_PJ2-4
TP 25PLL_SEL1J2-87
TP 26PLL_LOLNJ2-85
TP 27PLL_RSTJ2-89
TP 28DX_PJ2-119
TP 29DX_NJ2-121
TP 30IN1_NJ2-6
TP 31B505_CLK0_PJ2-10
TP 32B505_CLK0_NJ2-12
TP 33B505_CLK1_PJ2-16
TP 34B505_CLK1_NJ2-18
TP 35B128_CLK1_PJ2-22
TP 36B128_CLK1_NJ2-24
TP 37CLK0_NJ2-1
TP 38CLK0_PJ2-3
TP 39CLK8_PJ2-7
TP 40CLK8_NJ2-9
TP 41CLK7_PJ2-13
TP 42CLK7_NJ2-15
TP 43IN2_PJ3-66
TP 44IN2_NJ3-68
TP 45B230_CLK1_NJ3-59
TP 46B230_CLK1_PJ3-61
TP 47B229_CLK0_NJ3-65
TP 48B229_CLK0_PJ3-67
TP 49PLL_3V3J3-152
TP 50GNDJ3-155
TP 51PL_1V8J1-121
TP 52PS_1V8J3-147
TP 53SI_PLL_1V8J3-151
TP 54PROG_BJ2-100
TP 55...56GND-


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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Chip/InterfaceDesignatorNotes
DIP SwitchS1...3
LEDsD2...4Red LEDs
OscillatorU2125.00 MHz


DIP Switch

There are three DIP Switches, S1, S2, S3.

The Boot Mode can be set through DIP Switch S1, refer to BootMode table.

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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titleMIOs pins

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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Chip/InterfaceDesignatorNotes

Quad SPI Flash Memory

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Notes :

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DIP Switch S1Signals

B2B

Notes
S1AMODE0J2-109
S1BMODE1J2-107
S1CMODE2J2-105
S1DMODE3J2-103


Control signals must be set using DIP Switch S2, S3.

U?? Pin
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MIO Pin
DIP Switch S2
Schematic
SignalsB2BNotes

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S2AEN_PSGTJ2-84Position OFF enables power rail
S2BEN_GT_RJ2-95Position OFF enables power rail
S2CEN_GT_LJ2-97Position OFF enables power rail
S2DEN_PLL_PWRJ2-77Position OFF enables power rail, connected to PG_PL
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Notes
MIO PinSchematicU? Pin