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Figure 1: TE0705-04 Block Diagram.
Main Components
Figure 2: 4 x 5 SoM carrier board TE0705-04.
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- ARM JTAG Connector (DS-5 D-Stream) J15 - PJTAG to EMIO multiplexing needed
- 12-pin IDC header socket J1 (right angle, max. VCCIO voltage 3.3V)
RJ45 GbE Connector
- SD Card Socket - Zynq SDIO0 bootable SD port
- 12-pin IDC header socket (right angle) J2
- Micro USB Connector J12 (Device, Host or OTG Modes)
- Battery holder for CR1220 (RTC backup voltage)
- 12-pin IDC header socket (vertical) J5
- 12-pin IDC header socket (vertical) J6
- User Push-Button S2 ("RESTART" button by default)
- User Push-Button S1 ("RESET" button by default)
- User LEDs D6, D7, D8, D9
- User LEDs D4, D5, D14, D15
- Mini USB Connector (USB JTAG and UART Interface) J7
- User 4-bit DIP-Switch S3
- User 4-bit DIP-Switch S4
- FTDI FT2232HQ FT2232H USB 2.0 High Speed to UART/FIFO
- Lattice Semiconductor MachXO2 1200HC System Controller CPLD
- Jumper J4 to fix user button S2 to switched state
- 40-Pin-Header J13 for access to PL IO-bank-pins
- 40-Pin-Header J11 for access to PL IO-bank-pins
- Samtec Razor Beam™ LSHM-150 B2B connector JB1
- Samtec Razor Beam™ LSHM-150 B2B connector JB2
- Samtec Razor Beam™ LSHM-130 B2B connector JB3
- Barrel jack for 12V power supply J10
- Jumper J21 to select supply voltage of VIOTB
- Jumper J9, J19, J20 to select supply voltage of USB-VBUS
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- Overvoltage, undervoltage and reverse supply protection controller
- Barrel jack for 12V power supply
- On-board System Controller CPLD (Lattice MachXO2 1200HC), programmable via Mini-USB JTAG interface J7
- SoM can be programmed via ARM JTAG interface connector (J15) or through System Controller CPLD via Mini-USB JTAG interface J7
- RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs
- 2 x 40-pin headers J11 and J13 for access to module's PL IO bank pins
- USB JTAG/UART interface (FTDI FT2232HQFT2232H) with Mini-USB connector J7
- 8 x user LEDs (red) routed to System Controller CPLD
- 2 x user-push buttons routed to System Controller CPLD. By default (depending on CPLD firmware) configured as system "RESET" and "RESTART" buttons
- 2 x 4-bit DIP-switch for baseboard configuration
- 2 x 12-pin IDC header socket (vertical) J5, J6 for accessing module's PL IO bank pins, can be used as LVDS pairs
- 2 x 12-pin IDC header socket (right angle) J1 and J2 for accessing module's PL IO bank pins or PS MIO0 bank pins (if used with Zynq module)
- 2 x 50-pin IDC header J11, J13 for accessing module's PL IO bank pins
- Micro SD card socket with card detect switch, can be used for system booting
- Micro-USB interface (J12) connected to SoM's USB transceiver (Device, Host or OTG modes)
- Trenz Electronic 4 x 5 cm module connectors (3 x Samtec LSHM series)
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Micro SD card socket is connected to the B2B connector through a Texas Instruments TXS02612 SDIO Port Expander for voltage translation. The Micro SD card has 3.3V signal voltage level while Xilinx Zynq MIO bank uses 1.8V for VCCIO.
Dual
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Channel USB to UART/FIFO
The TE0701 TE0705 carrier board has on-board USB 2.0 High Speed high-speed to UART/FIFO IC FT2232HQ FT2232H from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program the System Controller CPLD, . Channel B can be used as UART Interface routed to CPLD. There are also 6 additional bus-lanes available for user-specific use.
There is also a standard 256 Byte -byte serial EEPROM connected to the FT2232HQ-chip available to store custom configuration settings.FT2232H chip pre-programmed with license code to support Xilinx programming tools.
| Warning |
|---|
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content |
| Note |
| Warning: When using FTDI software tools, the 256-byte user EEPROM can be erased without confirmation. As a consequence, the Digilent license stored in the EEPROM will also be deleted . |
USB Interface
The TE0705 carrier board has two USB connectors:
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JTAG Interface
JTAG access to the on-board System Controller CPLD and SoM is provided via mini-USB JTAG interface J7 (FTDI FT2232H) and controlled by DIP switch S3-3. To enable JTAG port of the CPLD, set switch S3-3 JTAGEN to OFF
| S3-3 Position | Description |
|---|---|
| ON | Enable JTAG interface for SoM via B2B connector JB2. |
| OFF | Enable JTAG interface for on-board System Controller CPLD. |
LEDs
There are eight LEDs (D6, D7, D8, D9, D4, D5, D14, D15) available to the user. All LEDs are red colored and mapped to the on-board System Controller CPLD. Their functions are programmable and depend on the firmware of the System Controller CPLD. For detailed information, please refer to the documentation of the TE0705 System Controller CPLD.
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An exception here is the 'MIO12'-pin, which is buffered with a Schmitt-Trigger buffer with a hysteresis of 5.0V.
IDC header socket J2
12-pin header J2 provides access to SoM's PL IO-bank pins are accessible on socket J2. The IO-signals are routed from this socket to B2B-connector JB3 and are only single-. Operable with fixed (3.3V) or adjustable VCCIO voltage VIOTB (Single ended IOs, hence this signal-pins are not usable as differential pairs. Maximal VCCIO voltage is VIOTB on this socketLVDS pairs).
40-pin headers J11 and J13
40-Pin-Header pin header J11 and J13 for provide access to SoM's PL IO-bank - pins on routed to B2B-connectors JB1 and JB2. Operable with fixed (3.3V) or adjustable VCCIO voltage VIOTB (Single ended IOs, not usable as LVDS pairs, only single-ended IOs).
operable with fixed (3.3V) or adjustable IO-voltage VIOTB (not usable as LVDS pairs, only single-ended IOs).
Power and Power and Power-On Sequence
Power Supply
Single 12V power supply with minimum current capability of 3A is recommended to operate the board.
Power-On Sequence
The All on-board voltages of the carrier board will be powered up simultaneously after one when single power-supply with a nominal voltage of 12V is connected to the power-jack J10.
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The purpose of the jumper and the DIP-switch S3 of the Carrier Board will be explained in the following sections.
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VCCIO
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Voltage Level DIP-Switch S3
There is the possibility to select the module's PL IO-bank's supply voltage VIOTB to fixed adjustable voltages FMC_VADJ. Therefore, the jumper J21 has to be set to the position 1, 2-3, to connect the pins 'VIOTB' and 'ADJ'. On position 1-2, 3, the supply voltage VIOTB will be fixed to 3.3V
Table 3 shows the switch-configuration of the DIP-switch S3 to set the voltage FMC_VADJ.
Note: The configuration With jumper J21, user can select between two different power sources for SoM PL IO banks supply voltage VIOTB. If set to position 1-2, fixed 3.3V is selected as VIOTB source. If set to position 2-3, FMC_VADJ is selected as VIOTB source. Voltage level of FMC_VADJ depends on the used firmware of the System Controller CPLD. For detailed information, refer to the documentation of the TE0705 System Controller CPLD.settings of DIP-switch S3, see table below:
| J21 Position |
|---|
S3-1 (CM1) | S3-2 ( |
|---|
CM0) | FMC_VADJ |
|---|
Voltage | VIOTB Voltage | Notes | |||
|---|---|---|---|---|---|
| 1-2 | - | - | - | 3.3V | |
| 2-3 | OFF | OFF | 1.8V | 1.8V | |
| 2-3 | OFF | ON | 2.5V | 2.5V | |
| 2-3 | ON | OFF | 3.3V | 3.3V | |
| 2-3 | ON | ON | 1.8V |
| 1.8V | This setting also enables JTAG access to the System Controller CPLD on the SoM via B2B connector JB2. |
Table 3: Jumper J21 and DIP-switch S3 settings for VIOTB voltage configuration.
Note: Exact function of the S3-1 and S3-2 switches depend on the TE0705 System Controller CPLD firmware. For more detailed information, refer to the documentation of the TE0705 System Controller CPLD.Table 3: Switch S3 positions for fixed values of the FMC_VADJ voltage
Configuring Power Supply of the Micro USB Connector (Device, Host or OTG Modes)
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Additionally, the TE0705 carrier board is equipped with a second mini USB port J7 that is connected to a "USB to multi-purpose UART/FIFO IC" from FTDI (FT2232HQFT2232H) and provides a USB-to-JTAG interface between a host PC and the TE0705 carrier board and the mounted SoM, respectively. Because it acts as a USB function device, no power switch is required (and only a ESD protection must be provided) in this case.
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| Date | Revision | Notes | PCN | Documentation link |
|---|---|---|---|---|
| 2016-10-04 | 04 | |||
| - | 03 | |||
| - | 02 | |||
| - | 01 |
Figure 5: Hardware revision number.
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| Date | Revision | Contributors | Description | ||||
|---|---|---|---|---|---|---|---|
| 2017-02-09 | Ali Naseri, Jan Kumann | TRM for TE0705-04 | 2017-01-15 | 0.1 | Ali Naseri | Initial document.
Disclaimer
| Include Page | ||||
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