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Refer to https://wiki.trenz-electronic.de/display/PD/TE0841+TRM for online version of this manual and additional technical documentation of the product.
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The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale KU035 FPGA, 2 banks of 512 MByte DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.
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For detailed information about the pin out, please refer to the Pin-out Tables.
I2C Interface
There are two PL bank 65 IO pins (PLL_SCL and PLL_SDA) reserved as I2C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I2C bus slave address is 0x70.
Additionally, two PL bank 65 IO pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I2C connectivity, otherwise these pins are ordinary IOs.
JTAG Interface
JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.
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| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| JTAGMODE | Input | JTAG select | Low for normal operation. |
| NRST_SC0 | Input | Reset | |
| SC1 | - | - | Not used by default. |
| SC2 | - | - | Not used by default. |
| SC3 | - | - | Not used by default. |
| SC4 | - | - | Not used by default. |
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On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Green | System Controller CPLD, bank 3 | Exact function is defined by SC CPLD firmware. |
I2C Interface
There are two PL bank 65 IO pins (PLL_SCL and PLL_SDA) reserved as I2C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I2C bus slave address is 0x70.
Additionally, two PL bank 65 IO pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I2C connectivity, otherwise these pins are ordinary IOs.
On-board Peripherals
Processing System (PS) Peripherals
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* TBD - To be determined soon with reference design setup.
Power-On Sequence
For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
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Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
VIN supply voltage | V | - | ||
| Supply voltage for HR I/O banks (VCCO) | –0.500 | 3.400 | V | See Xilinx datasheet DS892. |
Supply voltage for HP I/O banks (VCCO) | –0.500 | 2.000 | V | See Xilinx datasheet DS892. |
| I/O input voltage for HR I/O banks | –0.400 | VCCO + 0.550 | V | See Xilinx datasheet DS892. |
I/O input voltage for HP I/O banks | –0.550 | VCCO + 0.550 | V | See Xilinx datasheet DS892. |
GTH and GTY transceivers receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.500 | 1.260 | V | See Xilinx datasheet DS892. |
Storage temperature | -40 | +85 | °C | - |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | ||||
| Supply voltage for HR I/O banks (VCCO) | 1.140 | 3.400 | V | See Xilinx datasheet DS892. |
Supply voltage for HP I/O banks (VCCO) | 0.950 | 1.890 | V | See Xilinx datasheet DS892. |
I/O input voltage | –0.200 | VCCO + 0.20 | V | See Xilinx datasheet DS892. |
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-06-1214 | Jan Kumann | Initial document. |
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