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The B2B connectors J1 and J2 provide also access to the MGT - banks of the Zynq UltrascaleUltraScale+ MPSoC. There are 8 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).

The MGT - banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT - lanes are available on the B2B connectors:

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Table 3: B2B connector pin-outs of available MGT - lanes of the MPSoC

              1) Bank 224 only available at ZU4CG or ZU4EV MPSoC

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Configuration Bank Control Signals

The Xilinx Zynq UltrascaleUltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B-connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltrascaleUltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

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Analog Input

The Xilinx Zynq UltrascaleUltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

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MIOSignal Schematic NameU7 Pin MIOSignal Schematic NameU17 Pin
0SPI Flash-SCK/M4B2 7SPI Flash-SCKC2
1SPI Flash-DQ1/M1D2 8SPI Flash-DQ0/M0D3
2SPI Flash-DQ2/M2C4 9SPI Flash-DQ1/M1D2
3SPI Flash-DQ3/M3D4 10SPI Flash-DQ2/M2C4
4SPI Flash-DQ0/M0D3 11SPI Flash-DQ3/M3D4
5SPI Flash-SCKC2 12SPI Flash-SCK/M4B2

Table 7: MIO - pin assignment of the Quad SPI Flash memory ICs

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The boot source of the Zynq Ultrascale UltraScale MPSoC can be selected via 4 dedicated pins, which generate a 4-bit code to select the boot mode. The pins are accessible on B2B connector J2:

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Following boot modes are possible on the TE0803 Ultrascale UltraScale module by generating the corresponding 4-bit code by the pins 'PS_MODE0' ... 'PS_MODE3' (little-endian alignment):

Boot ModeMode Pins [3:0]MIO LocationDescription
JTAG0x0JTAGDedicated PS interface.
QSPI320x2MIO[12:0]

Configured on module with dual QSPI Flash Memory.

32-bit addressing.
Supports single and dual parallel
configurations.
Stack and dual stack is not
supported.

SD00x3MIO[25:13]Supports SD 2.0.
SD10x5MIO[51:38]Supports SD 2.0.
eMMC_180x6MIO[22:13]Supports eMMC 4.5 at 1.8V.
USB 00x7MIO[52:63]Supports USB 2.0 and USB 3.0.
PJTAG_00x8MIO[29:26]PS JTAG connection 0 option.
SD1-LS0xEMIO[51:39]

Supports SD 3.0 with a required
SD 3.0 compliant level shifter.

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For Functional details see  ug1085 - Zynq ultrascale UltraScale TRM (Boot Modes Section).

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SignalB2B Connector pinFunction
PLL_SCL / PLL_SDAJ2-90 / J2-92

I²C interface, extern external pull-ups needed for SCL- /SDA - line.

I²C address in current configuration: 1110000b

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The TE0803-01 SoM is equipped with two on-board oscillators to provide the Zynq 's MPSoC's PS configuration bank 503 with reference clock-signals.

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This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltrascaleUltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular extern DCDC converters.

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Each Power Domain has its own "Enabling"- and "Power Good"-signals. The power rail 'GT_DCDC' is only necessary for variants of the TE0803 module with the Xilinx Zynq UltrascaleUltraScale+ ZU4CG or ZU4EV MPSoC to generate the voltages for the available Xilinx GTH unit.

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There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC DC-DC converters, which power up further DCDC DC-DC converters and the particular on-board voltages:

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The TE0803 SoM meets the recommended criteria to power up the Xilinx Zynq UltrascaleUltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DCDC DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The on-board voltages of the TE0803 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DCDC DC-DC converters. The on-board voltages will be powered up at three steps.

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Following diagram clarifies the sequence of enabling the three power instances utilizing the DCDC DC-DC converter control signals ('Enable', 'Power-Good'), which will power-up in descending order as listed in the blocks of the diagram.

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Figure 4: Power-On Sequence Utilizing DCDC DC-DC Converter Control Signals

Operation Conditions of the

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DC-DC Converter Control Signals

The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good-Signals need extern external pull-up resistors.

Enable-SignalB2B Connector PinMax. VoltageNote Power-Good-SignalB2B Connector PinPull-up ResistorNote
EN_LPDJ2-1086VTPS82085SIL data sheet LP_GOODJ2-1064K7, pulled up to LP_DCDC-
EN_FPDJ2-102DCDCINNC7S08P5X data sheet PG_FPDJ2-1104K7, pulled up to DCDCIN-
EN_PLJ2-101max PL_DCINleft floating for logic high
(drive to GND for logic low)
 PG_PLJ2-104extern external pull-up needed (max. voltage 'GT_DCDC'),
max. sink current 1 mA

TPS82085SIL /
NC7S08P5X data sheet

EN_DDRJ2-112DCDCINNC7S08P5X data sheet PG_DDRJ2-1144K7, pulled up to DCDCIN-
EN_PSGTJ2-84DCDCINNC7S08P5X data sheet PG_PSGTJ2-82extern external pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74801 data sheet
EN_GT_RJ2-95GT_DCDCNC7S08P5X data sheet PG_GT_RJ2-91extern external pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74401 data sheet
---- PG_VCU_1V0J2-97

extern external pull-up needed (max. 5.5V),
max. sink current 1 mA

TPS82085SIL data sheet

Table 16: Recommended operation conditions of DCDC DC-DC converter control signals

 

Warning
To avoid any demages damage to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/O's should be tri-stated during power-on sequence.

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Variants Currently In Production

0°C 100°Cextended
Module VariantZynq UltrascaleUltraScale+ ModuleVideo Codec UnitGTH Transceiver UnitZynq Ultrascale+ Module Junction TemperatureOperating Temperature RangeTransceivers
TE0803-TE0803-01-02CG-1EXCZU2CG-1SFVC784E---
TE0803-01-03CG-1EXCZU3CG-1SFVC784E--0°C - 100°Cextended
TE0803-01-04CG-1E 1)XCZU4CG-1SFVC784E-yes0°C - 100°Cextended
TE0803-01-02EG-1EXCZU2EG-1SFVC784E--0°C - 100°Cextended
TE0803-01-03EG-1EXCZU3EG-1SFVC784E--0°C - 100°Cextended
TE0803-01-04EV-1E 1)XCZU4EV-1SFVC784Eyesyes0°C - 100°Cextended

Table 19: Differences between variants of Module module TE0803-01 variants

                1) Not yet available

All variants are rated for Extended temperature range (0 - 100 °C).

Technical Specifications

Absolute Maximum Ratings

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Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C100°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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 DateRevisionContributorsDescription

Page info
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Jan Kumann

New smaller images

Temperature information changes.

Few corrections.

 

Page info
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V.4

 

Ali NaseriCurrent TRM release
2017-05-10v.1Ali NaseriInitial document

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