Versions Compared

Old Version 7

changes.mady.by.user Jan Kumann

Saved on

compared with

New Version 8

changes.mady.by.user Jan Kumann

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Scroll Only (inline)
Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803" for downloadable version of this manual and the rest of available documentation.
The Trenz Electronic TE0803 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+, max. 8 GByte DDR4 SDRAM with 64-Bit width databus data bus connection, max. 512 MByte SPI Boot Flash memory for configuration and operation, up to 8 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

...

  1. Xilinx ZYNQ UltraScale+ MPSoC, U1
  2. 2-Input AND Gate, U39
  3. Red LED (DONE), D1
  4. 256Mx16 DDR4-2400 SDRAM, U12
  5. 256Mx16 DDR4-2400 SDRAM, U9
  6. 256Mx16 DDR4-2400 SDRAM, U2
  7. 256Mx16 DDR4-2400 SDRAM, U3
  8. 12A PowerSoC DCDC DC-DC converter, U4
  9. 1.5A LDO DCDC DC-DC converter, U10
  10. 1.5A LDO DCDC DC-DC converter, U8
  11. Voltage monitor circuit, U41
  12. 0.35A LDO DCDC DC-DC converter, U26
  13. 0.35A LDO DCDC DC-DC converter, U27
  14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  18. 4-channel programmable PLL clock generator, U5
  19. Low-power programmable oscillator @ 25.000000 MHz, U5
  20. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
  21. 256 Mbit serial NOR Flash memory, U7
  22. 256 Mbit serial NOR Flash memory, U17

...

Each connector has a specific arrangement of the signal-pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq UltrascaleUltraScale+ MPSoC like I/O-banks, interfaces and Gigabit transceivers
or to the on-board peripherals.

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS - pairs or single ended I/O's to the B2B connectors.

...

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO0 ...MIO5 and MIO7 ...MIO12.

B2
MIOSignal Schematic NameU7 PinU7 Pin Name MIOSignal Schematic NameU17 PinU17 Pin Name
0SPI Flash-SCK/M4B2CLK 7SPI Flash-SCKC2C2CS#
1SPI Flash-DQ1/M1D2DO/IO1D2 8SPI Flash-DQ0/M0D32SPI Flash-DQ2/M2D3DI/IO0
2C4WP#/IO2C4 9SPI Flash-DQ1/M1D2
3SPI Flash-DQ3/M3D4 10SPI Flash-DQ2/M2C4
4SPI Flash-DQ0/M0D3 11SPI Flash-DQ3/M3D4
D2DO/IO1
3D4HOLD#/IO3 10C4WP#/IO2
4D3DI/IO0 11D4HOLD#/IO3
5C2CS# 12B2CLK5SPI Flash-SCKC2 12SPI Flash-SCK/M4B2

Table 7: MIO pin assignment of the Quad SPI Flash memory ICs

...

yyyy-MM-dd08-06

17

 DateRevisionContributorsDescription

page2017-info

modified-datemodified-datedateFormat
Jan Kumann

New smaller images.

New QSPI Flash MIO mapping table.

Temperature information changes.

Few corrections.

 

page2017-infomodified05-date

modified-date
dateFormatyyyy-MM-dd
V.4

 

Ali NaseriCurrent TRM release.
2017-05-10v.1Ali NaseriInitial document.

Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices