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Additional assembly options for cost or performance optimization plus high volume prices are available on request.

Block Diagram

Figure 1: TE0841-01 block diagram.

Main Components

Image Modified   Image Removed Image Added

Figure 2: TE0841-01 main components.

  1. Xilinx Kintex UltraScale FPGA, U1
  2. Ultra performance oscillator @25.000000 MHz, U3
  3. 12A PowerSoC DC-DC converter (0.95V), U14
  4. 12A PowerSoC DC-DC converter (0.95V), U7
  5. Low-jitter precision LVDS oscillator @200.0000 MHz, U11
  6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
  7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
  8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
  11. Programmable quad clock generator, U2
  12. 32 MByte QSPI Flash, U6
  13. 4 Gbit DDR4 SDRAM, U4
  14. 4 Gbit DDR4 SDRAM, U5
  15. System Controller CPLD, U18
  16. Low-dropout (LDO) linear regulator (MGTAUX), U9
  17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

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Storage device name

Content

Notes

OTP Flash area

Empty

Not programmed.
Quad clock generator  

Table 1: TE0841-01 module initial delivery state of programmable on-board devices.

Signals, Interfaces and Pins

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ParameterMinMaxUnitsReference Document
VIN supply voltage   V 
Supply voltage for HR I/O banks (VCCO)1.140
3.400
VSee Xilinx datasheet DS892.
Supply voltage for HP I/O banks (VCCO)
0.950
1.890
VSee Xilinx datasheet DS892.
I/O input voltage
–0.200
VCCO + 0.20VSee Xilinx datasheet DS892.

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

2017-06-14

Jan Kumann
Initial document.

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