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The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale KU035 FPGA, 2 banks 1 GByte of 512 MByte DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.
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Board to Board (B2B) I/Os
Table below lists bank number, bank type, B2B connection, I/O signals connected from the SoCs signal/LVDS pair count and power source for each SoC PL I/O banks and bank connected to the B2B connectors:
FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes | ||||||
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64 | HR | JM1 | 48 IOs, 24 LVDS pairs | B64_VCCO | B64_VCCO supplied by the carrier board. | ||||||
65 | HR | JM1 | 8 IOs | 3.3V | 224 | MGT | JM1 | 3 lanes | Powered by on-module power supply. | ||
65 | HR | JM3 | 4 IOs, 2 LVDS pairs | 3.3V | Powered by on-module power supply. | ||||||
66 | HP | JM3 | 16 IOs, 8 LVDS pairs | B66_VCCO | B66_VCCO supplied by the carrier board | ||||||
224 | MGT | JM3 | 1 lane | ||||||||
225 | MGT | JM3 | 4 lanes | ||||||||
67 | HP | JM2 | 48 IOs, 24 LVDS pairs | B67_VCCO | B67_VCCO supplied by the carrier board | ||||||
67 | HP | JM2 | 2 IOs | B67_VCCO | B67_VCCO supplied by the carrier board | ||||||
68 | HP | JM2 | 18 IOs, 9 LVDS pairs | B68_VCCO | B68_VCCO supplied by the carrier board |
Table 2: General overview of SoC's PL I/O signals connected to the B2B connectors.
For detailed information about the pin out, please refer to the Pin-out Tables.
MGT Lanes
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
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0 | 225 | GTH |
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1 | 225 | GTH |
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2 | 225 | GTH |
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3 | 225 | GTH |
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4 | 224 | GTH |
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5 | 224 | GTH |
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6 | 224 | GTH |
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7 | 224 | GTH |
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Table 3: MGT lanes
Below is listed MGT banks reference clock sources. Note that clocks consists of...
Bank | Clock Signal | Source | FPGA Pin |
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224 | MGT_CLK2 | ||
224 | MGT_CLK3 | ||
225 | MGT_CLK0 | ||
225 | MGT_CLK1 |
Table 4: MGT reference clock sources.
JTAG Interface
JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.
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