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The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale KU035 FPGA, 2 banks 1 GByte of 512 MByte DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.

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Board to Board (B2B) I/Os

Table below lists bank number, bank type, B2B connection, I/O signals connected from the SoCs signal/LVDS pair count and power source for each SoC PL I/O banks and bank connected to the B2B connectors: 

Table 2: General overview of SoC's PL I/O signals connected to the B2B connectors.

For detailed information about the pin out, please refer to the Pin-out Tables. 

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 3: MGT lanes

Below is listed MGT banks reference clock sources. Note that clocks consists of...

Table 4: MGT reference clock sources.

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

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