Page History
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Clock signal | Bank | Source | FPGA Pin | Notes |
---|---|---|---|---|
MGT_CLK0_P | 225 | B2B, JM3-33 | MGTREFCLK0P_225, Y6 | Supplied by the carrier - board. |
MGT_CLK0_N | 225 | B2B, JM3-31 | MGTREFCLK0N_225, Y5 | Supplied by the carrier - board. |
MGT_CLK1_P | 225 | U2, CLK1B | MGTREFCLK1P_225, V6 | On-board Si5338A. |
MGT_CLK1_N | 225 | U2, CLK1A | MGTREFCLK1N_225, V5 | On-board Si5338A. |
MGT_CLK2_P | 224 | B2B, JM3-34 | MGTREFCLK2P_224, AD6 | Supplied by the carrier - board. |
MGT_CLK2_N | 224 | B2B, JM3-32 | MGTREFCLK2N_224, AD5 | Supplied by the carrier - board. |
MGT_CLK3_P | 224 | U2, CLK2B | MGTREFCLK3P_224, AB6 | On-board Si5338A. |
MGT_CLK3_N | 224 | U2, CLK2B | MGTREFCLK3N_224AB5224, AB5 | On-board Si5338A. |
Table 4: MGT reference clock sources.
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Note |
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JTAGMODE pin 89 in B2B connector JM1 should be kept set low or grounded for normal operation. |
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Clock Signal | Frequency | Source | FPGA | Notes |
---|---|---|---|---|
- | 25.000000 MHz | SiT8208 (U3), CLK | - | Reference clock input for Si5338 PLL quad clock generator. |
CLK200M | 200.0000 MHz | DSC1123 (U11), OUT | R25/R26, bank 45 | |
CLK0 | User programmable | Si5338 (U2), CLK3 | T24/T25, bank 45 | |
CLK1 | User programmable | Si5338 (U2), CLK0 | R23/P23, bank 45 | |
MGT_CLK0 | Supplied by the carrier board | JM3-31, JM3-33 | Y5/Y6, bank 225 | Bank 225 MGTs clock source from baseboard. |
MGT_CLK1 | User programmable | Si5338 (U2), CLK1 | V5/V6, bank 225 | Bank 225 MGTs clock source from on-board PLL quad clock generator. |
MGT_CLK2 | Supplied by the carrier board | JM3-32, JM3-34 | AD6/AD5, bank 224 | Bank 224 MGTs clock source from baseboard. |
MGT_CLK3 | User programmable | Si5338 (U2), CLK2 | AB6/AB5, bank 224 | Bank 224 MGTs clock source from on-board PLL quad clock generator. |
Oscillators
The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
Clock Source | Frequency | Signal Name | Clock Destination |
---|---|---|---|
U3, SiT8208AI | 25.000000 MHz | CLK | U2, pin 3 (IN3) |
U11, DSC1123DL5 | 200.0000 MHz | CLK200M_P | U1, pin R25 |
U11, DSC1123DL5 | 200.0000 MHz | CLK200M_N | U1, pin R26 |
On-board LEDs
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Green | System Controller CPLD, bank 3 | Exact function is defined by SC CPLD firmware. |
Power and Power-On Sequence
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Overview
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