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Additionally, two PL bank 65 IO pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I2C connectivity, otherwise these pins are ordinary IOs.
On-board Peripherals
Processing System (PS) Peripherals
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System Controller CPLD
The System Controller CPLD (U18) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed information, refer to the reference page of the SC CPLD firmware of this module.
Quad SPI Flash Memory
On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
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Clocking
| Clock Signal | Frequency | Source | FPGA | Notes |
|---|---|---|---|---|
| - | 25.000000 MHz | SiT8208 (U3), CLK | - | Reference clock input for Si5338 PLL quad clock generator. |
| CLK200M | 200.0000 MHz | DSC1123 (U11), OUT | R25/R26, bank 45 | |
| CLK0 | User programmable | Si5338 (U2), CLK3 | T24/T25, bank 45 | |
| CLK1 | User programmable | Si5338 (U2), CLK0 | R23/P23, bank 45 | |
| MGT_CLK0 | Supplied by the carrier board | JM3-31, JM3-33 | Y5/Y6, bank 225 | Bank 225 MGTs clock source from baseboard. |
| MGT_CLK1 | User programmable | Si5338 (U2), CLK1 | V5/V6, bank 225 | Bank 225 MGTs clock source from on-board PLL quad clock generator. |
| MGT_CLK2 | Supplied by the carrier board | JM3-32, JM3-34 | AD6/AD5, bank 224 | Bank 224 MGTs clock source from baseboard. |
| MGT_CLK3 | User programmable | Si5338 (U2), CLK2 | AB6/AB5, bank 224 | Bank 224 MGTs clock source from on-board PLL quad clock generator. |
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The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
| Clock Source | Frequency | Signal Name | Clock Destination |
|---|---|---|---|
| U3, SiT8208AI | 25.000000 MHz | CLK | U2, pin 3 (IN3) |
| U11, DSC1123DL5 | 200.0000 MHz | CLK200M_P | U1, pin R25 |
| U11, DSC1123DL5 | 200.0000 MHz | CLK200M_N | U1, pin R26 |
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Green | System Controller CPLD, bank 3 | Exact function is defined by SC CPLD firmware. |
Power and Power-On Sequence
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Overview
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