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| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| JTAGMODE | Input | JTAG select | Low for normal operation. |
| NRST_SC0 | Input | Reset | |
| SC1 | - | - | Not used by default. |
| SC2 | - | - | Not used by default. |
| SC3 | - | - | Not used by default. |
| SC4 | - | - | Not used by default. |
Quad SPI
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Interface
On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Quad SPI Flash (U6) is connected to the FPGA configuration bank 0.
| Signal Name | U6 Pin | FPGA Pin |
|---|---|---|
| SPI_CS | C2 | RDWR_FCS_B_0, AH7 |
| SPI_D0 | D3 | D00_MOSI_0, AA7 |
| SPI_D1 | D2 | D01_DIN_0, Y7 |
| SPI_D2 | C4 | D02_0, U7 |
| SPI_D3 | D4 | D03_0, V7 |
| SPI_CLK | B2 | CCLK_0, V11 |
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Green | System Controller CPLD, bank 3 | Exact function is defined by SC CPLD firmware. |
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Overview
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