Page History
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| Signal Name | U6 Pin | FPGA Pin |
|---|---|---|
| SPI_CS | C2 | RDWR_FCS_B_0, AH7 |
| SPI_D0 | D3 | D00_MOSI_0, AA7 |
| SPI_D1 | D2 | D01_DIN_0, Y7 |
| SPI_D2 | C4 | D02_0, U7 |
| SPI_D3 | D4 | D03_0, V7 |
| SPI_CLK | B2 | CCLK_0, V11 |
On-board LEDs
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I2C Interface
There are two PL bank 65 IO pins (PLL_SCL and PLL_SDA) reserved as I2C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I2C bus slave address is 0x70.
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| Clock Source | Frequency | Signal Name | Clock Destination |
|---|---|---|---|
| U3, SiT8208AI | 25.000000 MHz | CLK | U2, pin 3 (IN3) |
| U11, DSC1123DL5 | 200.0000 MHz | CLK200M_P | U1, pin R25 |
| U11, DSC1123DL5 | 200.0000 MHz | CLK200M_N | U1, pin R26 |
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Green | System Controller CPLD, bank 3 | Exact function is defined by SC CPLD firmware. |
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Overview
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