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On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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Programmable PLL Clock

Module has Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate .

Si5338A Pin
Signal Name / Description
Connected ToDirectionNote

IN1

-

Not connected.Input

-

IN2-GNDInput-

IN3

Reference input clock.

U3, pin 3Input25.000000 MHz oscillator, Si8208AI.

IN4

-GNDInputLSB (pin 'IN4') of the default I2C address 0x70 not activated.

IN5

-

Not connected.Input-
IN6-GNDInput-

CLK0A

CLK1_P

U1, R23Output

FPGA bank 45.

CLK0BCLK1_NU1, P23OutputFPGA bank 45.
CLK1AMGTCLK1_N Output 
CLK1BMGTCLK1_P Output 
CLK2AMGTCLK3_N Output 
CLK2BMGTCLK3_P Output 
CLK3A

CLK0_P

U1, pin T24Output

FPGA bank 45.

CLK3BCLK0_NU1, pin T25OutputFPGA bank 45.
Clock SignalFrequencySourceFPGANotes
-

25.000000 MHz

SiT8208 (U3), CLK-Reference clock input for Si5338 PLL quad clock generator.
CLK200M200.0000 MHzDSC1123 (U11), OUTR25/R26, bank 45 
CLK0User programmableSi5338 (U2), CLK3T24/T25, bank 45 
CLK1User programmableSi5338 (U2), CLK0R23/P23, bank 45 
MGT_CLK0Supplied by the carrier boardJM3-31, JM3-33Y5/Y6, bank 225Bank 225 MGTs clock source from baseboard.
MGT_CLK1User programmableSi5338 (U2), CLK1V5/V6, bank 225Bank 225 MGTs clock source from on-board PLL quad clock generator.
MGT_CLK2Supplied by the carrier boardJM3-32, JM3-34AD6/AD5, bank 224Bank 224 MGTs clock source from baseboard.
MGT_CLK3User programmableSi5338 (U2), CLK2AB6/AB5, bank 224Bank 224 MGTs clock source from on-board PLL quad clock generator.

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