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JTAG Signal

B2B Connector Pin

TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99

Table 5: JTAG interface signals.


Note
JTAGMODE pin 89 in B2B connector JM1 should be set low or grounded for normal operation.

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Module has Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate .

Si5338A Pin
Signal Name / Description
Connected ToDirectionNote

IN1

-

Not connected.Input
-

Not used.

IN2-GNDInput
-
Not used.

IN3

Reference input clock.

U3, pin 3Input25.000000 MHz oscillator, Si8208AI.

IN4

-GNDInput
LSB (pin 'IN4') of the default
I2C slave device address
0x70 not activated
LSB.

IN5

-

Not connected.Input
-
Not used.
IN6-GNDInput
-
Not used.

CLK0A

CLK1_P

U1, R23Output

FPGA bank 45.

CLK0BCLK1_NU1, P23OutputFPGA bank 45.
CLK1A
MGTCLK1
MGT_CLK1_N
 
U1, V5Output
 
FPGA MGT bank 225 reference clock.
CLK1B
MGTCLK1
MGT_CLK1_P
 
U1, V6Output
 
FPGA MGT bank 225 reference clock.
CLK2A
MGTCLK3
MGT_CLK3_N
 
U1, AB5Output
 
FPGA MGT bank 224 reference clock.
CLK2B
MGTCLK3
MGT_CLK3_P
 
U1, AB6Output
 
FPGA MGT bank 224 reference clock.
CLK3A

CLK0_P

U1, pin T24Output

FPGA bank 45.

CLK3BCLK0_NU1, pin T25OutputFPGA bank 45.
Clock SignalFrequencySourceFPGANotes
-

25.000000 MHz

SiT8208 (U3), CLK-Reference clock input for Si5338 PLL quad clock generator.
CLK200M200.0000 MHzDSC1123 (U11), OUTR25/R26, bank 45 
CLK0User programmableSi5338 (U2), CLK3T24/T25, bank 45 
CLK1User programmableSi5338 (U2), CLK0R23/P23, bank 45 
MGT_CLK0Supplied by the carrier boardJM3-31, JM3-33Y5/Y6, bank 225Bank 225 MGTs clock source from baseboard.
MGT_CLK1User programmableSi5338 (U2), CLK1V5/V6, bank 225Bank 225 MGTs clock source from on-board PLL quad clock generator.
MGT_CLK2Supplied by the carrier boardJM3-32, JM3-34AD6/AD5, bank 224Bank 224 MGTs clock source from baseboard.
MGT_CLK3User programmableSi5338 (U2), CLK2AB6/AB5, bank 224Bank 224 MGTs clock source from on-board PLL quad clock generator.

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