Versions Compared

Old Version 27

changes.mady.by.user Jan Kumann

Saved on

compared with

New Version 28

changes.mady.by.user Jan Kumann

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

FPGA BankTypeB2B ConnectorI/O Signal CountVoltageNotes
64HRJM148 IOs, 24 LVDS pairsB64_VCCOB64_VCCO supplied Supplied by the carrier board.
65HRJM18 IOs3.3VPowered by onOn-module power supply.
65HRJM34 IOs, 2 LVDS pairs3.3VPowered by onOn-module power supply.
66HPJM316 IOs, 8 LVDS pairsB66_VCCOB66_VCCO supplied Supplied by the carrier board
67HPJM248 IOs, 24 LVDS pairsB67_VCCOB67_VCCO supplied Supplied by the carrier board
67HPJM22 IOsB67_VCCOB67_VCCO supplied Supplied by the carrier board
68HPJM218 IOs, 9 LVDS pairsB68_VCCOB68_VCCO supplied Supplied by the carrier board

Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors.

...

On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Programmable PLL Clock

Module has There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

Si5338A Pin
Signal Name / Description
Connected ToDirectionNote

IN1

-

Not connected.Input

Not used.

IN2-GNDInputNot used.

IN3

Reference input clock.

U3, pin 3Input25.000000 MHz oscillator, Si8208AI.

IN4

-GNDInputI2C slave device address LSB.

IN5

-

Not connected.InputNot used.
IN6-GNDInputNot used.

CLK0A

CLK1_P

U1, R23Output

FPGA bank 45.

CLK0BCLK1_NU1, P23OutputFPGA bank 45.
CLK1AMGT_CLK1_NU1, V5OutputFPGA MGT bank 225 reference clock.
CLK1BMGT_CLK1_PU1, V6OutputFPGA MGT bank 225 reference clock.
CLK2AMGT_CLK3_NU1, AB5OutputFPGA MGT bank 224 reference clock.
CLK2BMGT_CLK3_PU1, AB6OutputFPGA MGT bank 224 reference clock.
CLK3A

CLK0_P

U1, pin T24Output

FPGA bank 45.

CLK3BCLK0_NU1, pin T25OutputFPGA bank 45.

...