Page History
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FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage | Notes |
---|---|---|---|---|---|
64 | HR | JM1 | 48 IOs, 24 LVDS pairs | B64_VCCO | B64_VCCO supplied Supplied by the carrier board. |
65 | HR | JM1 | 8 IOs | 3.3V | Powered by onOn-module power supply. |
65 | HR | JM3 | 4 IOs, 2 LVDS pairs | 3.3V | Powered by onOn-module power supply. |
66 | HP | JM3 | 16 IOs, 8 LVDS pairs | B66_VCCOB66 | _VCCO supplied Supplied by the carrier board |
67 | HP | JM2 | 48 IOs, 24 LVDS pairs | B67_VCCOB67 | _VCCO supplied Supplied by the carrier board |
67 | HP | JM2 | 2 IOs | B67_VCCOB67 | _VCCO supplied Supplied by the carrier board |
68 | HP | JM2 | 18 IOs, 9 LVDS pairs | B68_VCCOB68 | _VCCO supplied Supplied by the carrier board |
Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors.
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On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Programmable PLL Clock
Module has There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.
Si5338A Pin | Signal Name / Description | Connected To | Direction | Note |
---|---|---|---|---|
IN1 | - | Not connected. | Input | Not used. |
IN2 | - | GND | Input | Not used. |
IN3 | Reference input clock. | U3, pin 3 | Input | 25.000000 MHz oscillator, Si8208AI. |
IN4 | - | GND | Input | I2C slave device address LSB. |
IN5 | - | Not connected. | Input | Not used. |
IN6 | - | GND | Input | Not used. |
CLK0A | CLK1_P | U1, R23 | Output | FPGA bank 45. |
CLK0B | CLK1_N | U1, P23 | Output | FPGA bank 45. |
CLK1A | MGT_CLK1_N | U1, V5 | Output | FPGA MGT bank 225 reference clock. |
CLK1B | MGT_CLK1_P | U1, V6 | Output | FPGA MGT bank 225 reference clock. |
CLK2A | MGT_CLK3_N | U1, AB5 | Output | FPGA MGT bank 224 reference clock. |
CLK2B | MGT_CLK3_P | U1, AB6 | Output | FPGA MGT bank 224 reference clock. |
CLK3A | CLK0_P | U1, pin T24 | Output | FPGA bank 45. |
CLK3B | CLK0_N | U1, pin T25 | Output | FPGA bank 45. |
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