Page History

B47_L1_P ... B47_L12_P
B47_L1_N ... B47_L12_N

VCCO47
pins J3-43, J3-44

VCCO max. 3.3V
usable as single-ended I/O's

B48_L1_P ... B48_L12_P
B48_L1_N ... B48_L12_N

VCCO48
pins J3-15, J3-16

VCCO max. 3.3V
usable as single-ended I/O's

B64_L1_P ... B64_L24_P
B64_L1_N ... B64_L24_N

VCCO64
pins J4-58, J4-106

VCCO max. 1.8V
usable as single-ended I/O's

B_64_T0 ... B_64_T3pins J4-8, J4-6, J4-4, J4-2

VCCO64
pins J4-58, J4-106

VCCO max. 1.8V

usable as single-ended I/O's

B65_L1_P ... B65_L24_P
B65_L1_N ... B65_L24_N

B_65_T0 ... B_65_T3

VCCO65
pins J4-69, J4-105

VCCO max. 1.8V
usable as single-ended I/O's

B_65_T0 ... B_65_T3
pins J4-7, J4-5, J4-3, J4-1

VCCO65
pins J4-69, J4-105

B66_L1_P ... B66_L24_P
B66_L1_N ... B66_L24_N

VCCO66
pins J1-90, J1-120

VCCO max. 1.8V
usable as single-ended I/O's

B66_L1_P ... B66_L24_P
B66_L1_N ... B66_L24_N

B_66_T0 ... B_66_T3pins J1-147, J1-145, J1-143, J1-141

VCCO66
pins J1-90, J1-120

VCCO max. 1.8V
only usable as single-ended I/O's

4 GTH lanes

(4 RX / 4 TX)

B228_RX3_P, B228_RX3_N, pins J1-27, J1-29
B228_TX3_P, B228_TX3_N, pins J1-26, J1-28

B228_RX2_P, B228_RX2_N, pins J1-33, J1-35
B228_TX2_P, B228_TX2_N, pins J1-32, J1-34

B228_RX1_P, B228_RX1_N, pins J1-39, J1-41
B228_TX1_P, B228_TX1_N, pins J1-38, J1-40

B228_RX0_P, B228_RX0_N, pins J1-45, J1-47
B228_TX0_P, B228_TX0_N, pins J1-44, J1-46

1 reference clock signal (B228_CLK0) from B2B connector
J3 (pins J3-60, J3-62) to bank's pins R8/R7

1 reference clock signal (B228_CLK1) from programmable
PLL clock generator U5 to bank's pins N8/N7

4 GTH lanes

(4 RX / 4 TX)

B229_RX3_P, B229_RX3_N, pins J1-27, J1-29
B229_TX3_P, B229_TX3_N, pins J1-26, J1-28

B229_RX2_P, B229_RX2_N, pins J1-33, J1-35
B229_TX2_P, B229_TX2_N, pins J1-32, J1-34

B229_RX1_P, B229_RX1_N, pins J1-39, J1-41
B229_TX1_P, B229_TX1_N, pins J1-38, J1-40

B229_RX0_P, B229_RX0_N, pins J1-45, J1-47
B229_TX0_P, B229_TX0_N, pins J1-44, J1-46

1 reference clock signal (B229_CLK0) from B2B connector
J3 (pins J3-65, J3-67) to bank's pins L8/L7

1 reference clock signal (B229_CLK1) from programmable
PLL clock generator U5 to bank's pins J8/J7

4 GTH lanes

(4 RX / 4 TX)

B230_RX3_P, B230_RX3_N, pins J1-3, J1-5
B230_TX3_P, B230_TX3_N, pins J1-2, J1-4

B230_RX2_P, B230_RX2_N, pins J1-9, J1-11
B230_TX2_P, B230_TX2_N, pins J1-8, J1-10

B230_RX1_P, B230_RX1_N, pins J1-15, J1-17
B230_TX1_P, B230_TX1_N, pins J1-14, J1-16

B230_RX0_P, B230_RX0_N, pins J1-21, J1-23
B230_TX0_P, B230_TX0_N, pins J1-20, J1-22

1 reference clock signal (B230_CLK1) from B2B connector
J3 (pins J3-59, J3-61) to bank's pins G8/G7

1 reference clock signal (B230_CLK0) from programmable
PLL clock generator U5 to bank's pins E8/E7

4 GTH lanes

(4 RX / 4 TX)

B128_RX3_N, B128_RX3_P, pins J2-28, J2-30
B128_TX3_N, B128_TX3_P, pins J2-25, J2-27

B128_RX2_N, B128_RX2_P, pins J2-34, J2-36
B128_TX2_N, B128_TX2_P, pins J2-31, J2-33

B128_RX1_N, B128_RX1_P, pins J2-40, J2-42
B128_TX1_N, B128_TX1_P, pins J2-37, J2-39

B128_RX0_N, B128_RX0_P, pins J2-46, J2-48
B128_TX0_N, B128_TX0_P, pins J2-43, J2-45

1 reference clock signal (B128_CLK1) from B2B connector
J2 (pins J2-22, J2-24) to bank's pins D25/D26

1 reference clock signal (B128_CLK0) from programmable
PLL clock generator U5 to bank's pins F25/F26

4 GTR lanes

(4 RX / 4 TX)

B505_RX3_N, B505_RX3_P, pins J2-52, J2-54
B505_TX3_N, B505_TX3_P, pins J2-49, J2-51

B505_RX2_N, B505_RX2_P, pins J2-58, J2-60
B505_TX2_N, B505_TX2_P, pins J2-55, J2-57

B505_RX1_N, B505_RX1_P, pins J2-64, J2-66
B505_TX1_N, B505_TX1_P, pins J2-61, J2-63

B505_RX0_N, B505_RX0_P, pins J2-70, J2-72
B505_TX0_N, B505_TX0_P, pins J2-67, J2-69

2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector
J2 (pins J2-10/J2-12, J2-16/J2-18) to bank's pins P25/P26, M25/M26

2 reference clock signal (B505_CLK2, B505_CLK3) from programmable
PLL clock generator U5 to bank's pins K25/K26, H25/H26