Page History
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- Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
- 2 banks of 512 MByte, 16 bit wide DDR4 SDRAM
- 256 Mbit (32 MByte) QSPI Flash
- 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
- User I/O: 60 x HR , 84 I/Os
- 84 x HP I/Os
- Serial transceiver: 8 x GTH transceiver lanes (TX/RX)
- GT 2 x MGT external clock inputs: 2 - Clocking
- Si5338 - 4 output PLLs, GT and PL clocks
- 200 MHz LVDS oscillator - All power supplies on-board, single power source operation
- Evenly spread supply pins for optimized signal integrity
- Size: 40 x 50 mm
- 3 mm mounting holes for skyline heat spreader
- Rugged for industrial applications
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins pin connection information:
| Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
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| 0 | 225 | GTH |
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| 1 | 225 | GTH |
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| 2 | 225 | GTH |
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| 3 | 225 | GTH |
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| 4 | 224 | GTH |
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| 5 | 224 | GTH |
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| 6 | 224 | GTH |
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| 7 | 224 | GTH |
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