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The Trenz Electronic TEBF0808 carrier board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes. The carrier board has a Mini-ITX form factor making it capable to be fitted into a PC enclosure. On the PC enclosure's rear and front panel, essential data MGT interfaces and connectors are accessible, for the front panel elements there also Intel-PC compatible headers available for connecting the front panel elements to them.
Key Features
- Mini-ITX form factor, PC enclosure compatible
- ATX-24 power supply connector
- Optional 12V standard power plug
- Headers
- Intel 10-pin HDA Audio
- Intel 9-pin Power-/Reset-Button, Power-/HD-LED
- PC-BEEPER
- On-board Power- / Reset-Switches
- 2x Configuration 4-bit DIP-switches
- 2x Optional 4-wire PWM fan connectors
- PCIe Slot - one PCIe lane (16 lane connector)
- CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
- 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)
- Dual SFP+ Connector (2x1 Cage)
- One Display-Port 1x DisplayPort (single lane)
- One 1x SATA Connector
- 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
- 1x USB3.0 on-board header connector with two ports
- FMC HPC Slot (FMC_VADJ max. VCCIO)
- FMC Fan
- Gigabit Ethernet RGMII PHY with RJ45 MegJack
- All Carrier Board carrier board peripherals' I²C - interfaces muxed to MPSoC's I²C - interface on PS bank 503
- Quad programmable PLL clock generator SI5338A
- 2x SMA coaxial connectors for clock signals
- MicroSD- / MMC-Card Socket (bootable)
- 32 Gbit (4 GByte) on-board eMMC memory flash (8 banks a 4 Gbit)
- Two 2x System Controller CPLDs Lattice MachXO2 1200 HC
- One 1x Samtec FireFly (4 GT lanes bidirectional)
- One 1x Samtec FireFly connector for reverse loopback
- 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
- 20 Pin -pin ARM JTAG Connector (PS JTAG0)
- 3x PMOD connector (GPIO's and I²C interface to SC CPLDs / and MPSoC moduleCarrier SC CPLD managing power-up sequence of MPSoC module)
- On-board DC-DC PowerSoCs
Additional assembly options are available for cost or performance optimization upon request.
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- PMOD connector, P2
- MicroSD Card socket (on bottom side), J16
- Display Port socketDisplayPort connector, J13
- USB3.0 A 2x , RJ45 1x (stacked), J7
- SFP+ 2x1 cage, J14
- PCIe x16 connector (one PCIe lane connected), J11
- FMC HPC connector, J5
- FMC-Fan connector 5V, J19
- USB3.0 connector, J8
- PC-BEEPER 4-pin header, J23
- SMA coaxial connector (SI5338A clock output), J32
- SMA coaxial connector (clock input to MPSoC module), J33
- eMMC MMC Card socket, J27
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
- CAN bus 6-pin header, J29
- CAN bus 10-pin connector, J24
- ARM - JTAG 20-pin connector, J30
- ATX-24 power supply connector, J20
- 4-Wire PWM fan connector, J35
- JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
- JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
- Power Jack 2.1mm 12V, J25
- 4-bit DIP-switch, S5
- Power Button, S1
- Samtec FireFly Connector connector for reverse loopback, J21/J22
- Samtec FireFly Connector connector (4 GT lanes bidirectional), J6/J15
- SATA Headerheader, J31
- 4-Wire PWM fan connector, J26
- Programmable I²C interface of programmable on-module PLL I²C interface (10-pin header), J17
- Reset Button, S2
- INTEL HDA 9-pin header, J9
- Intel front panel (PWR-/RST-Button, HD-/PWR-LED) 9-pin header, J10
- Samtec FireFly Connector J6connector J6/J15 I²C interface (3-pin header), J34
- 4-bit DIP-switch, S4
- PMOD connector, P3
- PMOD connector, P1
- Battery Holder CR1220, B1
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Storage device name | Content | Notes |
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General Purpose Configuration User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT) | Not programmed | - |
USB3.0 HUB Configuration EEPROM (Microchip 24LC128-I/ST) | Not programmed | - |
Si5338A programmable PLL NVM OTP | Not programmed | - |
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The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are usable as LVDS-pairs.The I/O signals are routed from the FPGA banks as LVDS-pairs to the FMC connector.
Figure 3: FMC HPC Connector
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MGT Bank | Type | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs from FMC Connector |
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228 | GTH | 4 GTH lanes | B228_RX3_P, B228_RX3_N, pins J5-A10, J5-A11 B228_RX2_P, B228_RX2_N, pins J5-A6, J5-A7 B228_RX1_P, B228_RX1_N, pins J5-A2, J5-A3 B228_RX0_P, B228_RX0_N, pins J5-C6, J5-C7 | 1 reference clock signal (B228_CLK0) from FMC connector Si5345 CLK3 signal of prog. PLL on mounted SoM routed |
229 | GTH | 4 GTH lanes | B229_RX3_P, B229_RX3_N, pins J5-B12, J5-B13 B229_RX2_P, B229_RX2_N, pins J5-B16, J5-B17 B229_RX1_P, B229_RX1_N, pins J5-A18, J5-A19 B229_RX0_P, B229_RX0_N, pins J5-A14, J5-A15 | 1 reference clock signal (B229_CLK0) from FMC connector Si5345 CLK2 signel signal of prog. PLL on mounted SoM routed |
230 | GTH | 2 GTH lanes | B230_RX1_P, B230_RX1_N, pins J5-B4, J5-B5 B230_RX0_P, B230_RX0_N, pins J5-B8, J5-B9 | Si5345 CLK1 signal of prog. PLL on mounted SoM routed |
Table 3: FMC connector pin-outs of available MGT - lanes of the MPSoC
The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:
Clock Signal Schematic Name | FMC Connector Pins | Direction | Clock Source | Notes |
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B228_CLK0 | J5-D4 / J5-D5 | in | FMC Connector J5 | clock signal to MGT bank 228 |
B229_CLK0 | J5-B20 / J5-B21 | in | FMC Connector J5 | clock signal to MGT bank 229 |
FMCCLK2 | J5-K4 / J5-K5 | out | Carrier Board PLL SI5338A U35, CLK2 | - |
FMCCLK3 | J5-J2 / J5-J3 | out | Carrier Board PLL SI5338A U35, CLK3 | - |
B64_L14_P / B64_L14_N | J5-H4 / J5-H5 | in | FMC Connector J5 | bank 64 clock capable LVDS-pairinput pins |
B48_L6_P / B48_L6_N | J5-G2 / J5-G3 | in | FMC Connector J5 | bank 48 clock capable LVDS-pairinput pins |
Table 4: FMC connector pin-outs for reference clock output
The FMC connector provides further interfaces like ' JTAG ' and 'I²C' to the System Controller CPLDI²C interfaces:
Interfaces | I/O Signal Count | Pin schematic Names / FMC Pins | Connected to | Notes |
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JTAG | 5 | FMC_TCK, pin J5-D29 FMC_TMS, pin J5-D33 FMC_TDI, pin J5-D30 FMC_TDO, pin J5- D31 | SC CPLD U17, bank 1 | VCCIO: 3V3SB TRST_L, pin J5-D34 pulled-up to 3V3_PER |
I²C | 2 | FMC_SCL, pin J5-C30 FMC_SDA, pin J5-C31 | I²C Switch U16 | I²C-lines pulled-up to 3V3_PER |
Control Lines | 34 | FMC_PRSNT_M2C, pin J5-H2 FMC_PG_C2M, pin J5-D1 (3V3_PER pull-up) FMC_PG_M2C, pin J5-F1 (3V3_PER pull-up) FMC_CLK_DIR, pin J5-B1 (pulled-down to GND) | I²C I/O Expander U38 SC CPLD U39, bank 0 I²C I/O Expander U38 SC CPLD U17, bank 1 | 'PG' = 'Power Good'-signal 'C2M' = carrier to (mezzanineMezzanine) module 'M2C' = (mezzanineMezzanine) module to carrier |
Table 5: FMC connector pin-outs of available interfaces to the System Controller CPLD
Several VCCIO voltages are available on the FMC connector to operate the I/O's in order of the intended purposeon different voltage levels:
VCCIO Schematic Name | FMC Connector J5 Pins | Notes |
---|---|---|
12V | C35/C37 | extern 12V power supply |
3V3_PER | D32/D36/D38/D40/C39 | 3.3V peripheral supply voltage |
FMC_VADJ | H40/G39/F40/E39 | adjustable FMC VCCIO voltage, supplied by DC-DC converter U8 |
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MIO | Configured as | System Controller CPLD | Notes |
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0..12 | Dual QSPI | - | Dual Flash Memory on TE0808 SoM; Bootable |
13..23 | SD0: eMMC | - | eMMC Memory U2; Bootable |
24, 25 | - | CPLD (U39) MUXED | - |
26..29 | - | CPLD (U17 MUXED | Bootable JTAG (PJTAG0) possible |
30 | force reboot after FSBL-PLL config for PCIe | CPLD (U39) MUXED | - |
31 | PCIe reset | CPLD (U39) MUXED | - |
32 | - | CPLD (U39) MUXED | - |
33 | - | CPLD (U39) MUXED | - |
34..37 | - | CPLD (U39) MUXED | - |
38, 39 | I2C0 | - | - |
40 | forwarded to PWRLED_P / LED_P | CPLD (U39) MUXED | - |
41 | - | - | - |
42, 43 | UART0 | CPLD (U39) MUXED | - |
44 | SD_WP to FPGA | CPLD (U39) MUXED | - |
45..51 | SD1: SD | - | Bootable MikroSD / MMC Card |
52..63 | USB0 | - | - |
64..75 | GEM3 | - | Ethernet RGMII |
76, 77 | MDC / MDIO | - | Ethernet RGMII |
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- 4 USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
- SDIO port with muxed MikroSD and MMC Card Socketsocket
- Gigabit Ethernet interface connected per RGMII
- eMMC interface
- Master I²C interface to on-board peripherals
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Figure 4: TEBF0808 MIO Interfaces
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PS GT Bank 505 Interfaces
On the The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:
- SATA (PS GT bank 505, MGT2 Lane)
- Display-Port DisplayPort (PS GT bank 505, MGT3 Lane, only TX-pair routed)
- PCI Express (PS GT bank 505, MGT0 Lane)
Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
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PCIe | PS 0 | 100 MHz | Si5345 CLK0 signal of prog. PLL on mounted SoM | clock signal routed on carrier board to PCIe connector J1 |
USB3 | PS 1 | 100 MHz | Si5345 CLK4 signal of prog. PLL on mounted SoM | clock signal routed internally on-module, |
SATA | PS 2 | 150 MHz | On-board oscillator U23 | optional: Si5345 CLK4 signal of prog. PLL on mounted SoM |
DP.0 | PS 3 | 27 MHz | Si5345 CLK5 signal of prog. PLL on mounted SoM | DisplayPort GT SERDES clock signal, Si5345 CLK6 signal of prog. PLL on mounted SoM, |
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Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
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FireFly | B128 MGT Lanes 0..3 | - | Si5345 CLK6 signal of prog. PLL on mounted SoM | clock signal internally on-module routed to B128 |
SFP | B230 MGT Lane 2 | 125 / 156.25 MHz | Si5345 CLK7 signal of prog. PLL on mounted SoM | clock signal routed on carrier board to B230 |
SFP | B230 MGT Lane 3 | 125 / 156.25 MHz | Si5345 CLK7 signal of prog. PLL on mounted SoM | clock signal routed on carrier board to B230 |
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Additionally the carrier board provides PMOD connectors with GPIO and I²C interface. Following table:
PMOD | Interface | Connected with | Notes |
---|---|---|---|
P1 | GPIO | HP Bank 65 of MPSoC (4 I/O's, B65_T0 ... B65_T3), System Controller CPLD U17 (4 I/O's, EX_IO1 ... EX_IO4) | Voltage translation via IC U33 with direction control, only singled-ended signaling possible |
P2 | I²C | 8-channel I²C Switch U27 | Accessible on MPSoC's I²C interface through I²C switch U27 |
P3 | I²C | 8-channel I²C Switch U27 | Accessible on MPSoC's I²C interface through I²C switch U27 |
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Figure 7: TEBF0808 CAN Interfaces, PMOD
Intel-PC Compatible Headers and FAN Connectors
The TEBF0808 carrier board provides with its Mini-ITX form factor the possibility to encase the board in a PC Enclosure. For this purpose, the board is equipped with several Intel-PC compatible headers to connect them to the PC Enclosure.
Pins Headers are available for following PC front panel elements
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Following table gives an overview about the particular pins of the headers and a description about their functionalities:
Header | Pin Name | Function | Connected to | Notes |
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J10 | Pin 1, HD LED+ | HD LED Anode | SC CPLD U39 | Reset und Power Switch-pins are also connected to switch buttons S1 and S2 |
J9 | Pin 1, PORT1L | Microphone Jack Left Microphone Jack Right Audio Out Jack Left Audio Out Jack Right Jack Detect / Mic in Ground | 24-bit Audio Codec IC U3 | - |
J23 | Pin 1, 3V3SB Pin 4, S1 | 3.3V DC Supply PC compatible Beeper | SC CPLD U39 | - |
J26 | Pin 1, GND | Ground 12V DC Supply RPM PWM | SC CPLD U39 | 4-wire PWM FAN connector |
J35 | Pin 1, GND | Ground 12V DC Supply RPM PWM | SC CPLD U39 | 4-wire PWM FAN connector |
J19 | Pin 1, GND | Ground 5V DC Supply | Load Switch Q3 (5V DC) | 2-wire FAN connector Fan off/on switchable by signal 'FAN_FMC_EN' on SC CPLD U39 |
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The System Controller CPLDs will be programmed by the XMOD-Header J28 with in a cascaded JTAG chain as visualized in Figure 8. To program the System Controller CPLDs, the JTAG interface of these devices have to be activated by DIP-switch S4-3.
The 4 GPIO/UART pins (XMOD1_A/B/E/G) of the XMOD-Header J28 are routed to the System Controller CPLD U17.
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