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Storage device name | Content | Notes |
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| System Controller CPLD | Default firmware. | - |
| FPGA eFuse OTP cells | Empty | Note programmed. |
Quad SPI Flash OTP area | Empty | Not programmed. |
| Quad clock generator OTP area | Empty | Not programmed. |
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For detailed information about the pin out, please refer to the Pin-out Tables.
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MGT Lanes
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pin connection information:
| Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
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| 0 | 225 | GTH |
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| 1 | 225 | GTH |
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| 2 | 225 | GTH |
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| 3 | 225 | GTH |
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| 4 | 224 | GTH |
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| 5 | 224 | GTH |
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| 6 | 224 | GTH |
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| 7 | 224 | GTH |
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Table 3: MGT lanes.
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Below are listed MGT banks reference clock sources.
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Power Consumption
| Power Input Pin | Typical Current |
|---|---|
| VIN | TBD* |
| 3.3VIN | TBD* |
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Overview
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