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Figure 1: TE0841-01 block diagram.
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Main Components
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Storage device name | Content | Notes |
|---|---|---|
| System Controller CPLD | Default firmware. | - |
| FPGA eFuse OTP cells | Empty | Note programmed. |
Quad SPI Flash OTP area | Empty | Not programmed. |
| Quad clock generator OTP area | Empty | Not programmed. |
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For detailed information about the pin out, please refer to the Pin-out Tables.
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MGT Lanes
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pin connection information:
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