Page History

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• Xilinx Zynq UltraScale+ MPSoC 784-pin package (ZU3EG, option for  ZU5EV)
  • Dual Cortex-A53 64-bit ARM v8 application processing unit (APU)
  • Dual Cortex-R5 32-bit ARM v7 real-time processing unit (RPU)

  • Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:

    • PCI Express® interface version 2.1 compliant
    • SATA 3.1 specification compliant interface

    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
  • 132 x HP PL I/Os (3 banks)
  • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
  • 4 x serial PS GTR transceivers
• 32-Bit 1 GByte DDR4 SDRAM, 4 GByte maximum
• Dual parallel SPI boot Flash, 512 MByte maximum
• 4 GByte eMMC (up to 64 GByte)
• GT reference clock input
• PLL for GT clocks (optional external reference)
• Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
• MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
• Hi-speed USB 2.0 ULPI transceiver with full OTG support (Microchip USB3320C)
• Programmable quad clock generator
• Plug-on module with 2 x 100-pin and 1 x 60-pin high-speed hermaphroditic strips
• All power supplies on board
• Size: 50 x 40 mm

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On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C1 by default. I²C addresses Addresses for on-board I²C slave devices are listed in the table below:

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Section currently not complete.

DDR4 Memory

Section currently not completeBy default TE0820-02 module has two 16-bit wide Nanya NT5AD256M16B2 DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GByte on-board RAM. Different memory sizes are available optionally.

2 x 32 MByte Quad SPI Flash Memory

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There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.The default frequency of each clock at start up is detailed in the table 7.

Once running, the frequency and other parameters can be changed by programming the device using the I2C I²C bus connected between the FPGA (master) and clock generator (slave). Logic needs to be generated inside the FPGA to utilize I2C bus correctlyFor this, proper I²C bus logic has to be implemented in FPGA.

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