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Figure 3: TE0820-02 power distribution diagram.
Power-On Sequence
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For highest efficiency of on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning indicating that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.Section currently not complete.
Power Rails
| Power Rail Name on B2B Connector | JM1 Pins | JM2 Pins | Direction | Notes |
|---|---|---|---|---|
| VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board. |
| 3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. |
| 3.3VIN | 13, 15, 91 | - | Input | Supply voltage from the carrier board. |
| VCCO_64 | - | 7, 9 | Input | High performance I/O bank voltage. |
| VCCO_65 | - | 5 | Input | High performance I/O bank voltage. |
| VCCO_66 | 9, 11 | - | Input | High performance I/O bank voltage. |
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