Page History
...
Figure 3: FMC HPC Connector
| FPGA BankB2B | I/O Signal Count | LVDS-pairs count | VCCO bank Voltage | Reference Clock Input from FMC Connector | Notes | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| J1 | Bank 4820 | 24 | 10 | FMC_VADJ | - | bank's VREF-pin connected to FMC connector pin J5-H1 (VREF_A_M2C) | ||||
| J3 | 20 | 10 | 1 reference clock signal from FMC connector | - | Bank 64 | 46 | 23 | FMC_VADJ | 1 reference clock signal from FMC connector | bank's VREF-pin connected to FMC connector pin J5-H1 (VREF_A_M2C) |
| Bank 65 | 46 | 23 | FMC_VADJ | - | bank's VREF-pin connected to FMC connector pin J5-H1 (VREF_A_M2C) | |||||
G3) to clock capable PL bank pin-pair | - | |||||||||
| J4 | 92 | 46 | FMC_VADJ | 1 reference clock signal from FMC connector | Bank 66 | 48 | 24 | FMC_VADJ | - | bank's VREF-pin connected pin connected to FMC connector pin J5-H1 (VREF_A_M2C) |
...
The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connectors J5:
| MGT BankB2B | Type | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs from FMC Connector |
|---|---|---|---|---|
| 228J1 | GTH | 4 GTH lanes | B228_RX3_P, B228_RX3_N, pins J5-A10, J5-A11 B228_RX2_P, B228_RX2_N, pins J5-A6, J5-A7 B228_RX1_P, B228_RX1_N, pins J5-A2, J5-A3 B228_RX0_P, B228_RX0_N, pins J5-C6, J5-C7 | 1 reference clock signal (B228_CLK0) from FMC connector Si5345 CLK3 signal of SoM's prog. PLL routed on-module to bank's pins N8/N7 MGT bank
|
| J1229 | GTH | 4 GTH lanes | B229_RX3_P, B229_RX3_N, pins J5-B12, J5-B13 B229_RX2_P, B229_RX2_N, pins J5-B16, J5-B17 B229_RX1_P, B229_RX1_N, pins J5-A18, J5-A19 B229_RX0_P, B229_RX0_N, pins J5-A14, J5-A15 | 1 reference clock signal (B229_CLK0) from FMC connector Si5345 CLK2 signal of SoM's prog. PLL routed on-module to bank's pins J8/J7 -B20, J5-B21) to MPSoC's MGT bank
|
| J1230 | GTH | 2 GTH lanes | B230_RX1_P, B230_RX1_N, pins J5-B4, J5-B5 B230_RX0_P, B230_RX0_N, pins J5-B8, J5-B9 | Si5345 CLK1 signal of SoM's prog. PLL routed on-module to bank's pins E8/E7 |
Table 3: FMC connector pin-outs of available MGT lanes of the MPSoC
...
| Clock Signal Schematic Name | FMC Connector Pins | Direction | Clock Source | Notes |
|---|---|---|---|---|
| B228_CLK0 | J5-D4 / J5-D5 | in | FMC Connector J5 | Extern MGT clock signal to MGT bank 228 |
| B229_CLK0 | J5-B20 / J5-B21 | in | FMC Connector J5 | Extern MGT clock signal to MGT bank 229 |
| FMCCLK2 | J5-K4 / J5-K5 | out | Carrier Board PLL SI5338A U35, CLK2 | -Clock signal to Mezzanine module |
| FMCCLK3 | J5-J2 / J5-J3 | out | Carrier Board PLL SI5338A U35, CLK3 | -Clock signal to Mezzanine module |
| B64_L14_P / B64_L14_N | J5-H4 / J5-H5 | in | FMC Connector J5 | bank 64 clock capable input pinsLVDS Clock to PL bank |
| B48_L6_P / B48_L6_N | J5-G2 / J5-G3 | in | FMC Connector J5 | bank 48 clock capable input pinsLVDS Clock to PL bank |
Table 4: FMC connector pin-outs for reference clock output
...
| Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
|---|---|---|---|---|
| PCIe | PS 0 | 100 MHz | Si5345 CLK0 clock signal of SoM's prog. PLL | clock signal routed on carrier board to PCIe connector J1 |
| USB3 | PS 1 | 100 MHz | Si5345 CLK4 signal clock signal of SoM's prog. PLL | clock signal routed on-module, |
| SATA | PS 2 | 150 MHz | On-board oscillator U23 | optional: Si5345 CLK4 clock signal of SoM's prog. PLL |
| DP.0 | PS 3 | 27 MHz | Si5345 CLK5 signal clock signal of SoM's prog. PLL | DisplayPort GT SERDES clock signal, |
Table 8: PS GT Lane Assignment
...
| Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
|---|---|---|---|---|
| FireFly | B128 MGT Lanes 0..3 | - | Si5345 CLK6 clock signal of SoM's prog. PLL | clock signal on-module routed to B128MGT bank |
| SFP | B230 MGT Lane 2 | 125 / 156.25 MHz | Si5345 CLK7 clock signal of SoM's prog. PLL | clock signal routed on carrier board to B230MGT bank |
| SFP | B230 MGT Lane 3 | 125 / 156.25 MHz | Si5345 CLK7 clock signal of SoM's prog. PLL | clock signal routed on carrier board to B230MGT bank |
Table 9: MGT Lane Assignment
...
| PMOD | Interface | Connected to | Notes |
|---|---|---|---|
| P1 | GPIO | HP Bank 65 of MPSoC (4 I/O's, B65_T0 ... B65_T3), System Controller CPLD U17 (4 I/O's, EX_IO1 ... EX_IO4) | Voltage translation via IC U33 with direction control, only singled-ended signaling possible |
| P2 | I²C | 8-channel I²C Switch U27 | Accessible on MPSoC's I²C interface through I²C switch U27 |
| P3 | I²C | 8-channel I²C Switch U27 | Accessible on MPSoC's I²C interface through I²C switch U27 |
...
Programmable PLL Clock Generator
The TEBF0808 Carrier Board carrier board is equipped with a Silicon Labs I2C programmable quad PLL clock generator Si5338A (U35). It's output frequencies can be programmed by using the I2C bus with address 0x70.
...
| Si5338A (U35) Input | Signal Schematic Name | Note |
|---|---|---|
IN1/IN2 | CLK8CLK8C_P, CLK8CLK8C_N | Reference clock signal from Si5345 (CLK8 of of SoM's prog. PLL on mounted SoM) |
IN3 | reference clock signal from oscillator SiTime SiT8008BI (U7) | 25.000000 MHz fixed frequency. |
IN4/IN6 | pins pin put to GND | LSB (pin 'IN4') of the default I²C-adress 0x70 not activated. |
IN5/IN6 | pins not connected / put to GND | not used, differential feedback input- |
| Si5338A (U35) Output | Signal Schematic Name | Note |
CLK0 A/B | SC_CLK0 | Reference clock signal to SC CPLD U17 (single-ended signaling) |
CLK1 A/B | SC_CLK1 | Reference clock signal to SC CPLD U17 (single-ended signaling) |
CLK2 A/B | FMCCLK2_P, FMCCLK2_N | Clock signal routed to FMC connector J5, pins J5-K4 / J5-K5 |
| CLK3 A/B | FMCCLK3_P, FMCCLK3_N | Clock signal routed to FMC connector J5, pins J5-J2 / J5-J3 |
...
Overview
Content Tools