Page History

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On-board Peripheral	B2B	MPSoC Unit / SoM peripheral	Description	TRM Section
FMC HPC J5, 24 LVDS pairs (48 I/O's)	J1	PL Bank (FMC_VADJ)	PL I/O-bank pins, differential pairs	FMC HPC Connector
FMC HPC J5, GTH Interface	J1	MGT Bank	10 MGT Lanes	FMC HPC Connector
SFP+ 2x1 Cage J14	J1	MGT Bank	2 MGT Lanes to dual SFP+ Connector	MGT Interfaces SFP+ and FireFly
SMA Coax J33	J1	On-module PLL	SMA Coaxial Connector to on-module PLL Clock Input pin	Programmable PLL Clock Generator
FMC HPC J5 10 LVDS pairs (20 I/O's) 1 LVDS Clock to PL Bank 2 MGT Clocks to MGT Banks	J2	PL Bank (FMC_VADJ) MGT Bank	PL I/O-bank pins, differential pairs 1 clock capable PL bank pin-pair 2 MGT clock input pin-pairs	FMC HPC Connector Programmable PLL Clock Generator
24-bit Audio Codec U3	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board 24-bit Audio Codec	Intel-PC Compatible Headers and FAN Connectors 24-bit Audio Codec
10 I/O's to SC CPLD U17	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board System Controller CPLD U17	System Controller CPDLs
8 I/O's to SC CPLD U39	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board System Controller CPLD U39	System Controller CPDLs
SDIO Interface, SD- / MMC-Card Mux	J3	PS MIO	SDIO interface connected to SD- / MMC-Card socket	MIO Bank Interfaces SDIO Port Expander
Board Peripheral's I²C Interfaces muxed to MPSoC I²C	J3	PS MIO	MPSoC I²C interface configured as master connected to on-board slaves	MIO Bank Interfaces 8-Channel I²C Switches
4 MIO to SC CPLD U17	J3	PS MIO	Functionality depending on MPSoC and CPLD firmware	System Controller CPDLs
15 MIO to SC CPLD U39	J3	PS MIO	Functionality depending on MPSoC and CPLD firmware	System Controller CPDLs
Ethernet PHY RGMII	J3	PS MIO	Ethernet PHY U12 connected per RGMII	MIO Bank Interfaces Gigabit Ethernet PHY
eMMC Flash	J3	PS MIO	eMMC Flash memory interface on PS bank	MIO Bank Interfaces eMMC Memory
USB2.0 PHY ULPI	J2	PS MIO	USB2.0 PHY U9 connected per ULPI	MIO Bank Interfaces High-speed USB ULPI PHY
SAMTEC FireFly Connector J6/J15	J2	MGT Bank	MGT Lanes to Samtec FireFly connector	MGT Interfaces SFP+ and FireFly
JTAG Interface via XMOD Header J12	J2	PS Config	MPSoC USB programmable JTAG interface	PS GT MIO Bank Interfaces MIO Bank Interfaces JTAG Interface
USB3.0 Lane	J2	PSGT	USB3.0 PS MGT Lane	MIO Bank Interfaces PS GT Bank Interfaces
4-port USB3.0 Hub	-	-	USB3.0 (2.0 compatible) Hub with 4 ports	MIO Bank Interfaces 4-port USB3.0 Hub
USB3.0 / RJ45 GbE Connector J7, USB3.0 Connector J8	-	-	2-port USB3.0 / RJ45 GbE Connector (stacked)	MIO Bank Interfaces
25 SoM Control Signals to SC CPLDs U17 / U39	J2	On-module DC-DC converter, PLL clock generator	Control Signals, e.g. "Enable"- / "Power Good"- signals of DC-DC-converter and further on-module peripherals	Power Management-On Sequence Diagram Programmable PLL Clock Generator
150 MHz Osci Clock Input	J2	-	150 MHz SATA interface MGT clock	Oscillators
Signals DONE, INIT_B, SRST_B, ... to SC CPLD U39	J2	PS Config	MPSoC control signal for PS- / PL configuration	System Controller CPDLs
SATA Connector J31 PCIe Connector J1 DisplayPort J13	J2	PSGT	Connectors of the MGT based data interfaces	PS GT Bank Interfaces
PLL Clock Output to PCIe Interface On-board PLL U35 MGT Bank (B2B J3)	J2	On-module PLL clock generator	Reference clock signals of the on-module programmable PLL clock generator	Programmable PLL Clock Generator
4 I/O's to PMOD P2 via IC U33	J4	PL Bank (FMC_VADJ)	PL user I/O's accessible on PMOD connector P2	CAN FD Interface and PMOD Connectors
3 I/O's to SC CPLD U17 via IC U32	J4	PL Bank (FMC_VADJ)	PL user I/O's routed to System Controller CPLD U17	System Controller CPDLs
FMC HPC J5 46 LVDS pairs (92 I/O's) 1 LVDS Clock to PL Bank	J4	PL Bank (FMC_VADJ)	PL I/O-bank pins, differential pairs 1 clock capable PL bank pin-pair	FMC HPC Connector Programmable PLL Clock Generator

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B2B	I/O Signal Count	LVDS-pairs count	VCCO bank Voltage	Reference Clock Input from FMC Connector	Notes
J1	48	24	FMC_VADJ	-	bank's VREF-pin connected to FMC connector pin J5-H1 (VREF_A_M2C)
J3	20	10	FMC_VADJ	1 reference LVDS clock signal from FMC connector J5 (pins J5-G2, J5-G3) to clock capable PL bank pin-pair	-
J4	92	46	FMC_VADJ	1 reference LVDS clock signal from FMC connector J5 connectorJ5 (pins J5-H4, J5-H5) to clock capable PL bank pin-pair	bank's VREF-pin connected to FMC connector pin J5-H1 (VREF_A_M2C)

Table 2: FMC connector pin-outs of available logic banks of the MPSoC

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B2B

Type

Count of MGT Lanes

Schematic Names / Connector Pins

MGT Bank's Reference Clock Inputs from FMC Connector

J1

GTH

4 GTH lanes

B228_RX3_P, B228_RX3_N, pins J5-A10, J5-A11
B228_TX3_P, B228_TX3_N, pins J5-A30, J5-A31

B228_RX2_P, B228_RX2_N, pins J5-A6, J5-A7
B228_TX2_P, B228_TX2_N, pins J5-A26, J5-A27

B228_RX1_P, B228_RX1_N, pins J5-A2, J5-A3
B228_TX1_P, B228_TX1_N, pins J5-A22, J5-A23

B228_RX0_P, B228_RX0_N, pins J5-C6, J5-C7
B228_TX0_P, B228_TX0_N, pins J5-C2, J5-C3

1 reference MGT clock signal (B228_CLK0) from FMC connector
J5 (pins J5-D4, J5-D5) to MPSoC's MGT bank

J1

GTH

4 GTH lanes

B229_RX3_P, B229_RX3_N, pins J5-B12, J5-B13
B229_TX3_P, B229_TX3_N, pins J5-B32, J5-B33

B229_RX2_P, B229_RX2_N, pins J5-B16, J5-B17
B229_TX2_P, B229_TX2_N, pins J5-B36, J5-B37

B229_RX1_P, B229_RX1_N, pins J5-A18, J5-A19
B229_TX1_P, B229_TX1_N, pins J5-A38, J5-A39

B229_RX0_P, B229_RX0_N, pins J5-A14, J5-A15
B229_TX0_P, B229_TX0_N, pins J5-A34, J5-A35

1 reference MGT clock signal (B229_CLK0) from FMC connector
J5 (pins J5-B20, J5-B21) to MPSoC's MGT bank

J1

GTH

2 GTH lanes

B230_RX1_P, B230_RX1_N, pins J5-B4, J5-B5
B230_TX1_P, B230_TX1_N, pins J5-B24, J5-B25

B230_RX0_P, B230_RX0_N, pins J5-B8, J5-B9
B230_TX0_P, B230_TX0_N, pins J5-B28, J5-B29

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MIO	Configured as	System Controller CPLD	Notes
0..12	Dual QSPI	-	Dual Flash Memory on TE0808 / -03 SoM; Bootable
13..23	SD0: eMMC	-	eMMC Memory U2; Bootable
24, 25	-	CPLD (U39) MUXED	-
26..29	-	CPLD (U17 MUXED	Bootable JTAG (PJTAG0)
30	force reboot after FSBL-PLL config for PCIe	CPLD (U39) MUXED	-
31	PCIe reset	CPLD (U39) MUXED	-
32	-	CPLD (U39) MUXED	-
33	-	CPLD (U39) MUXED	-
34..37	-	CPLD (U39) MUXED	-
38, 39	I2C0	-	-
40	forwarded to PWRLED_P / LED_P	CPLD (U39) MUXED	-
41	-	-	-
42, 43	UART0	CPLD (U39) MUXED	-
44	SD_WP to FPGA	CPLD (U39) MUXED	-
45..51	SD1: SD	-	Bootable MikroSD / MMC Card
52..63	USB0	-	-
64..75	GEM3	-	Ethernet RGMII
76, 77	MDC / MDIO	-	Ethernet RGMII

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Si5338A (U35) Input	Signal Schematic Name	Note
IN1/IN2	CLK8C_P, CLK8C_N	Reference clock signal Clock signal of SoM's prog. PLL
IN3	reference clock signal from oscillator SiTime SiT8008BI (U7)	25.000000 MHz fixed frequency.
IN4	pin put to GND	LSB (pin 'IN4') of the default I²C-adress 0x70 not activated.
IN5/IN6	pins not connected / put to GND	not used, differential feedback input
Si5338A (U35) Output	Signal Schematic Name	Note
CLK0 A/B	SC_CLK0	Reference clock Clock signal to SC CPLD U17 (single-ended signaling)
CLK1 A/B	SC_CLK1	Reference clock Clock signal to SC CPLD U17 (single-ended signaling) negative complementary signal 'SC_CLK1_N' put out to SMA Coax J33
CLK2 A/B	FMCCLK2_P, FMCCLK2_N	Clock signal routed to FMC connector J5, pins J5-K4 / J5-K5
CLK3 A/B	FMCCLK3_P, FMCCLK3_N	Clock signal routed to FMC connector J5, pins J5-J2 / J5-J3

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Clock Source	Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U10	USB0_RCLK	52.000000 MHz	USB 2.0 transceiver PHY U9, pin 26
SiTime SiT8008BI oscillator, U13	ETH_CLK	25.000000 MHz	Gigabit Ethernet PHY U12, pin 34
SiTime SiT8008BI oscillator, U7	-	25.000000 MHz	Quad PLL clock generator U35, pin 3
DSC1123 oscillator, U23	B505_CLK1	150.0000 MHz	PS GT Bank 505, dedicated for SATA interface
DSC1123 oscillator, U6 optional, not equipped	B505_CLK0	100.0000 MHz	PS GT Bank 505, dedicated for USB interface
Silicon Labs 570FBB000290DG, U45 optional, not equipped	B47_L5 (LVDS)	250.MHz	HD PL Bank 47 clock capable input pins
SiTime SiT8008BI oscillator, U25	CLK_CPLD	25.576000 MHz	System Controller CPLD U35, pin 128

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8-Channel I²C Switches

All on-board peripherals's interfaces and on-module peripherals with exposed accessible I²C interface to B2B connectors are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.

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Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.

The I²C bus works internally on-module with reference voltage 1.8V, it is connected to the PS IMPSoC I²C interface via PS MIO bank 501, (pins MIO38 and , MIO39, ) configured as master.

MIO	Signal Schematic Name	Notes
38	I2C_SCL	1.8V reference voltage
39	I2C_SDA	1.8V reference voltage

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On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank 505 to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank 501.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

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Trenz Electronic Documentation

Versions Compared

Old Version 58

New Version 59

Key

8-Channel I²C Switches