Page History
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- Xilinx Zynq UltraScale+ MPSoC 784-pin package (ZU3EGZU2EG, option for ZU5EV)
- Dual Quad-core or dual-core Cortex-A53 64-bit ARM v8 application processing unit (APU) (depends on assembly variant CG,EG,EV)
- Dual Cortex-R5 32-bit ARM v7 real-time processing unit (RPU)
Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:
- PCI Express® interface version 2.1 compliant
- SATA 3.1 specification compliant interface
DisplayPort source-only interface with video resolution up to 4k x 2k
- USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
- 1 GB/s serial GMII interface
- 132 x HP PL I/Os (3 banks)
- 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
- 4 x serial PS GTR transceivers
- 1 GByte DDR4 SDRAM, 4 GByte maximum
- Dual parallel SPI boot Flash, 512 MByte maximum
- 4 GByte eMMC (up to 64 GByte)
- GT reference clock input
- PLL for GT clocks (optional external reference)
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- Hi-speed USB 2.0 ULPI transceiver with full OTG support (Microchip USB3320C)
- Programmable quad clock generator
- Plug-on module with 2 x 100-pin and 1 x 60-pin high-speed hermaphroditic strips
- All power supplies on board
- Size: 50 x 40 mm
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Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| John Hartfiel |
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| 2017-08-21 | v.34 | John Hartfiel | update "Initial delivery state" section | ||||||||
| 2017-08-21 | v.33 | Jan Kumann |
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2017-08-18 | v.7 | John Hartfiel |
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2017-08-07 | v.5 | Jan Kumann | Initial version. | ||||||||
All | Jan Kumann, John Hartfiel |
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