Page History

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• MPSoC: ZYNQ UltraScale+ ZU9EG 900 pin package
• Memory
  - 64-Bit DDR4, 8 GByte maximum
  - Dual SPI boot Flash in parallel, 512 MByte maximum
• User I/O
  - 65 x MIO, 48 x HD (all),  156 x HP (3 banks)
  - Serial transceiver: 4 x GTR + 16 x GTH
  - Transceiver clocks inputs and outputs
  - PLL clock generator inputs and outputs
• Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
• B2B connectors: 4 x 160 pin
• Si5345 - 10 output PLL
• All power supplies on board, single 3.3V power source required
  - 14 on-board DCDC DC-DC regulators and 13 LDOs
  - LP, FP, PL separately controlled power domains
• Support for all boot modes (except NAND) and scenarios
• Support for any combination of PS connected peripherals

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Figure 1: TE0808-04 Block Diagram.

Main Components

Figure 2: TE0808 MPSoC module.

1. Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
2. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
3. Red LED (DONE), D1
4. 256Mx16 DDR4-2400 SDRAM, U12
5. 256Mx16 DDR4-2400 SDRAM, U9
6. 256Mx16 DDR4-2400 SDRAM, U2
7. 256Mx16 DDR4-2400 SDRAM, U3
8. 12A PowerSoC DCDC converter, U4
9. Quartz crystal, Y1
10. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
11. 10-channel programmable PLL clock generator, U5
12. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
13. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Quartz crystal, Y2
17. 256 Mbit serial NOR Flash memory, U7
18. 256 Mbit serial NOR Flash memory, U17

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Table 1: Initial Delivery State of the flash memories.

Signals, Interfaces and Pins

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Table 2: B2B connector pin-outs of available PL and PS banks of the TE0808-04 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

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The B2B connector J1 and J2 provide also access to the MGT - banks of the Zynq UltrascaleUltraScale+ MPSoC. There are 20 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).

The MGT - banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT - lanes are available on the B2B connectors:

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Table 3: B2B connector pin-outs of available MGT - lanes of the MPSoC.

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage 'PS_1V8'.

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Table 4: B2B connector pin-out of JTAG interface.

Configuration Bank Control Signals

The Xilinx Zynq UltrascaleUltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B-connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltrascaleUltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

Table 5: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx Zynq UltrascaleUltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

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Table 7: PS MIO - pin assignment of the Quad SPI Flash memory ICs.

Boot Process

The boot source of the Zynq Ultrascale UltraScale MPSoC can be selected via 4 dedicated pins, which generate a 4-bit code to select the boot mode. The pins are accessible on B2B connector J2:

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Following boot modes are possible on the TE0808 Ultrascale UltraScale+ module by generating the corresponding 4-bit code by the pins 'PS_MODE0' ... 'PS_MODE3' (little-endian alignment):

Table 9: Selectable boot modes by dedicated boot mode pins.

For Functional functional details see  ug1085 - Zynq ultrascale UltraScale TRM (Boot Modes Section).

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Table 10: Peripherals connected to the PS MIO - pins.

DDR4 SDRAM

The TE0808-04 SoM is equipped with with four DDR4-2400 SDRAM modules with up to 8 GByte memory density. The SDRAM modules are connected to the Zynq MPSoC's PS DDR - controller (bank 504) with a 64-bit databus widthdata bus.

Refer to the Xilinx Zynq UltrascaleUltraScale+ data sheet DS925 to get information, if datasheet DS925 for more information on whether the specific package of the Zynq UltrascaleUltraScale+ MPSoC equipped on module supports the maximum data transmission rate of 2400 MByte/s.

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Table 11: Programmable PLL clock generator input/output.

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

Table 12: B2B connector pin-out of Si5345A programmable clock generator.

Si5345 OTP can only be programmed two times, as different user configurations may required different setup TE0808 is normally shipped with blank OTP.
For more information refer to Si5345 at SiLabs.

Oscillators

The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock - signals.

Table 13: Reference clock-signals to PS configuration bank 503.

On-board LEDs

Table 14: LED's description.

Power and Power-On Sequence

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The TE0808 module equipped with the Xilinx Zynq UltrascaleUltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltrascaleUltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular extern DCDC external DC-DC converters.

The Processing System contains three Power Domains:

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On the TE0808-04 SoM, following Power Domains power domains can be powered up individually with power rails available on the B2B connectors:

• Full-Power Domainpower domain, supplied by power rail 'DCDCIN'
• Low-Power Domainpower domain, supplied by power rail 'LP_DCDC'
• Programmable Logiclogic, supplied by power rail' PL_DCIN'
• Battery Power Domainpower domain, supplied by power rail 'PS_BATT'

Each Power Domain power domain has its own "Enabling"- and "Power Good"-enable and power good signals. The power rail 'GT_DCDC' is necessary for generating is needed to generate the voltages for the Multi Gigabit Transceiver units of the Zynq UltrascaleUltraScale+ MPSoC.

Power Distribution Dependencies

The power rails ' DCDCIN', ' LP_DCDC', ' PL_DCIN', ' PS_BATT ' have to be powered up on the assigned pins of the B2B connectors as listed on the section "Power Rails". Except 'PS_BATT' (see section "Recommended Operation Conditions"), all power-rails can be powered up, with from 3.3V power sources , also shared(also share the same source, if Power Domain power domain control is not required).

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC DC-DC converters, which power up further DCDC DC-DC converters and the particular on-board voltages:

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Figure 3: Power Distribution Diagram.

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The TE0808 SoM meets the recommended criteria to power up the Xilinx Zynq UltrascaleUltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DCDC DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The on-board voltages of the TE0808 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DCDC DC-DC converters. The on-board voltages will be powered up at three steps.

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Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance has to be asserted.

Following diagram clarifies describes the sequence of enabling the three power instances utilizing the DCDC DC-DC converter control signals ('Enable', ' Power-Good'), which will power-up in descending order as listed in the blocks of the diagram.

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Figure 4: Power-On Sequence Utilizing DCDC DC-DC Converter Control Signals.

Operation Conditions of the

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DC-DC Converter Control Signals

The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good -Signals signals need extern external pull-up resistors.

Table 16: Recommended operation conditions of DCDC DC-DC converter control signals.

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Voltage Monitor Circuit

The voltages ' LP_DCDC ' and ' LP_0V85 ' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Powerpower-Onon. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.

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Figure 5: Voltage monitor circuit

Power Rails

Table 17: Power rails of the MPSoC module on accessible connectors.

Bank Voltages

Table 18: Range of MPSoC module's bank voltages.

B2B connectors

Variants Currently In Production

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