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For detailed information about the pin-out, please refer to the Pin-out table.

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MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

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Table 4: MGT lanes.

 

Below are listed MGT banks reference clock sources.

Clock signalBankSourceFPGA PinNotes
B505_CLK0_P505B2B, JM3-31PS_MGTREFCLK0P_505, F23Supplied by the carrier board.
B505_CLK0_N505B2B, JM3-33PS_MGTREFCLK0N_505, F24Supplied by the carrier board.
B505_CLK1_P505U10, CLK2APS_MGTREFCLK1P_505, E21On-board Si5338A.
B505_CLK1_N505U10, CLK2BPS_MGTREFCLK1N_505, E22On-board Si5338A.
B505_CLK2_P505N/APS_MGTREFCLK2P_505, C21Not connected.
B505_CLK2_N505N/APS_MGTREFCLK2N_505, C22Not connected.
B505_CLK3_P505U10, CLK1APS_MGTREFCLK3P_505, A21On-board Si5338A.
B505_CLK3_N505U10, CLK1BPS_MGTREFCLK3N_505, A22On-board Si5338A.

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Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

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System Controller I/O Pins

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Date

Revision

Contributors

Description

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modified-date
modified-date
dateFormatyyyy-MM-dd

v.39

Jan KumannMGT lanes section added.

2017-08-24

v.36

John Hartfiel

Correction in the  "Key Features" section.

2017-08-21v.34John Hartfiel"Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.

 

2017-08-18

v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

Initial version.

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