Page History

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1. Xilinx Zynq UltraScale+ ZU3EG MPSoC, U1
2. 4A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
3. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (PS_AVCC, 0.9V), U9
4. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (PS_AVTT, 1.8V), U13

5. 3A PFET load switch with configurable slew rate, fast transient isolation and hysteresis control (3.3V), Q1

6. Ultra-low supply-current voltage monitor with optional watchdog, U19
7. Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
8. Low-power programmable oscillator @ 12.000000 MHz, U11
9. Miniature traceability S/N pad for low-cost, unique product identification
10. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (DDR_2V5, 2.5V), U4
11. 4 Gbit (256 x 16) DDR4 SDRAM, U3
12. 4 Gbit (256 x 16) DDR4 SDRAM, U2
13. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (DDR_1V2, 1.2V), U15
14. 1.8V, 256 Mbit multiple I/O serial flash memory, U17
15. 1.8V, 256 Mbit multiple I/O serial flash memory, U7
16. Low-power programmable oscillator @ 33.333333 MHz, U32
17. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (PS_VCCINT, 0.85V), U12
18. 350 mA, ultra-low VIN, RF low-dropout linear regulator with bias pin (PS_PLL, 1.2V), U23
19. 3A high-efficiency step-down converter MicroSiP™ with integrated inductor (1.8V), U20
20. B2B connector Samtec Razor Beam™ LSHM-150, JM2
21. DDR termination regulator with VTTREF buffered reference, U16
22. Low-power programmable oscillator @ 52.000000 MHz, U14
23. Highly integrated full featured hi-speed USB 2.0 ULPI   transceiver, U18
24. B2B connector Samtec Razor Beam™ LSHM-130, JM3
25.  I²C programmable, any  frequency , any output  quad clock generator, U10
26. B2B connector Samtec Razor Beam™ LSHM-150, JM1
27. Lattice Semiconductor MachXO2 System Controller CPLD, U21
28. 4 GByte eMMC memory, U6
    

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The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

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There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Other two clocks Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

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