Page History
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| JTAGEN | PRSNT_TOP | CPLD_IO1 | Description |
|---|---|---|---|
| 1 | don't care | don't care | CPLD is in the JTAG Chain |
| 0 | 0 | 0 | Only Module FPGA is in the JTAG Chain |
| 0 | 0 | 1 | Module FPGA and FMC J6 are in the JTAG Chain. Note FMC J6 Chain must be closed. |
| 0 | 1 | 0 | Only Module FPGA is in the JTAG Chain |
| 0 | 1 | 1 | Only Module FPGA is in the JTAG Chain |
CPLD_IO2 is one, if second module is present and CPLD_IO1 is set one. , otherwise it's zero.
Appx. A: Change History and Legal Notices
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV01 | REV01 |
| REV01 working in processfinished | ||||||||||||||||||||||
| 2017-09-09 | v.1 | REV01 | REV01 |
| Initial release | ||||||||||||||||||||||
| All |
|
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Overview
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