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Following table describes the possible operation modes of the TE0790 adapter board. The operation modes are determined by the configuration of the FT2232H (done by programing the Configuration EEPROM) and the firmware implementation of the System Controller CPLD:
| # | FTDI Channel A | FTDI Channel B | Pins A to G | Notes |
|---|---|---|---|---|
| 1 | JTAG/SPI (MPSSE) | UART | JTAG, UART | JTAG compatible to Xilinx, Lattice and open-source software that uses FTDI MPPSE |
| 2 | JTAG/SPI (MPSSE) | JTAG/SPI (MPSSE) | JTAG, JTAG | Dual JTAG, only Channel A is Xilinx compatible |
| 3 | UART | UART | UART, UART | Dual UART |
| 4 | I2C | UART | I2C, UART | |
| 5 | MPSSE | 8x GPIO | ||
| 6 | UART | 8x GPIO | ||
| 7 | UART | UART | not used | UART to UART loopback |
| 8 | not used | Fast Serial | FTDI 4-wire fast serial adapter, custom EEPROM is needed to enable this mode | |
| 9 | CPLD update only | not used | user defined | Standalone Module with CPLD and 8 user programmable I/O |
Table 1: Initial delivery state of programmable devices on the module.
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- FTDI FT2232H IC U4
- 2x6 Pin Header (2.54mm, female), J2
- Mini USB B Connector J4
- Microchip 93AA56BT-I/OT Configuration EEPROM, U10
- DIP-switch S2
- Push button S1
- Lattice Semiconductor LCMXO2-256HC System Controller CPLD, U1
- SiTime SiT8008AI-73 oscillator @12MHz, U6
- Green LED, D1 (Power)
- Red LED, D4 (User)
- Red LED, D3 (UART RX)
- Red LED, D2 (UART TX)
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
| Configuration EEPROM U10 | variant depending | only programmed on TE-0790-xx, not programmed on TE0790-xxL |
Table 2: Initial delivery state of programmable devices on the module.
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The 2x6 pin header (2.54mm grid size, female) J2 have to be connected to the corresponding pin header on the target system. The signal assignment of the pin header on the adapter board depends on the configuration of the System Controller CPLD firmware.
Basic pin assignment:
| Signal | J2 Pin Name | J2 Pin Name | Signal |
|---|---|---|---|
| GND | 1* | GND | |
| User Defined | C | A | User Defined |
| VIO | VDD 3.3V | ||
| User Defined | D | B | User Defined |
| User Defined | F | E | User Defined |
| User Defined | H | G | User Defined / Button (Reset_n) |
Table 3: Pin header J2 signal assignment. *pin 1 on header J2
Figure 3: J2 pin header signal assignment
The signals of the FTDI FT2232H chip are not directly connected to the pin header J2 but routed to the System Controller CPLD of the adapter board, which controls and by-passes the signals to the pin header J2.
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Signal assignment on TE0790 CPLD - XMOD Standard:
| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI |
|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | |||
| ADBUS0 | TCK (output from adapter) | C | A | up | UART RXD (input to adapter) | BDBUS1 | |
| VIO | - | - | VDD 3.3V | ||||
| ADBUS2 | TDO (input to adapter) | up | D | B | UART TXD (output from adapter) | BDBUS0 | |
| ADBUS1 | TDI (output from adapter) | F | E | down | LED | ||
| ADBUS3 | TMS (output from adapter) | H | G | up | Button (Reset_n) |
Table 4: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2
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This is the same as the standard configuration except that UART RXD and TXD pins are swapped.
| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI |
|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | |||
| ADBUS0 | TCK (output from adapter) | C | A | UART TXD (output from adapter) | BDBUS0 | ||
| VIO | - | - | VDD 3.3V | ||||
| ADBUS2 | TDO (input to adapter) | up | D | B | up | UART RXD (input to adapter) | BDBUS1 |
| ADBUS1 | TDI (output from adapter) | F | E | down | LED | ||
| ADBUS3 | TMS (output from adapter) | H | G | up | Button (Reset_n) |
Table 5: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2
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On DIPFORTy, VIO Pin is connected with VDD 3.3V Pin. UART RXD is connected to FPGA-Pin L13 and UART TXD to K15. Connect XMOD on the top-side (FPGA side) of the PCB.
| FTDI | Signal | Pull up/down | J2 Pin Name | J2 Pin Name | Pull up/down | Signal | FTDI |
|---|---|---|---|---|---|---|---|
| GND | - | 1* | - | GND | |||
| BDBUS1 | UART RXD (input to adapter) | up | C | A | TCK (output from adapter) | ADBUS0 | |
| VIO | - | - | VDD 3.3 V | ||||
| BDBUS0 | UART TXD (output from adapter) | D | B | TMS (output from adapter) | ADBUS3 | ||
| ADBUS1 | TDI (output from adapter) | F | E | up | TDO (input to adapter) | ADBUS2 | |
| not used | H | G | CPLD User LED 'ULED' |
Table 6: Pin header J2 signal assignment with DIPFORTy firmware.
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Further functionalities are to secure the EEPROM content and to enable configuring the SC CPLD by JTAG interface:
| S2 | ON | OFF | Default | Description |
|---|---|---|---|---|
| 1 | Normal mode | Module update mode | ON | Update Mode JTAG access to SC CPLD only |
| 2 | Do not use | Normal mode | OFF | Do not change from default, secure configuration EEPROM |
| 3 | VIO connected to 3.3V | Power VIO from pin header J2 | OFF | SC CPLD I/O-voltage from/to pin header |
| 4 | Power 3.3V from USB | Power 3.3V from pin header J2 | OFF | Power on-board peripherals (FTDI chip & SC CPLD, ...) |
Table 7: DIP-switch S2 setting description.
The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switches S2-3 and S2-4:
| S2-3 | S2-4 | 3.3V (VCC) Pin 5 | VIO Pin 6 | Description |
|---|---|---|---|---|
| OFF | OFF | 3.3V from base | VIO from base | 3.3V (pin 5) and VIO (pin 6) sourced from base |
| OFF | ON | 3.3V from USB | VIO from base | VIO sourced from base by Pin 6 |
| ON | OFF | 3.3V from base | 3.3V from base | VIO sourced by Pin 5 and drive Pin 6 |
| ON | ON | 3.3V from USB | 3.3V from USB | VIO sourced by USB and drive Pin 6 |
Table 8: DIP-switch S2 power setting description.
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The on-board LEDs indicates system status data transmission activities:
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | Green | 3.3V | 3.3V power status LED |
| D2 | Red | FTDI IC, 'RXLED' | UART receive data activity |
| D3 | Red | FTDI IC, 'TXLED' | UART transmit data activity |
| D4 | Red | SC CPLD, 'ULED' | user LED, on standard SC CPLD firmware assigned to pins E and G, in DIPFORTy to G |
Table 9: On-board LEDs.
Power and Power-On Sequence
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The adapter on-board's peripherals are powered with 3.3V as supply voltage. If 3.3V (VCC and VIO ) is supplied only by the LDO DCDC U3 (S2-3 and S2-4 OFFON), the I/O-pins of header J2 deliver max. ~100mA.
If module is powered from base then S2-4 (and most likely S2-3 (VIO) too) must be OFF.
Following diagram shows how the settings of the DIP-switches S2-2 and S2-4 determines the configuration of the on-board voltages:
Figure 4: TE0790 on-board voltages configuration
Power Rails
Power Rail Name | Pin Header J2 | Direction | Notes |
|---|---|---|---|
| 3.3V | pin 5 | both possible |
| on-board peripherals' VCC and core voltages | ||
| VIO | pin 6 | both possible |
| Pin header J2 interface signals and SC CPLD VCCIO |
power Table 10: Module power rails.
Variants Currently In Production
Module Variant | Xilinx Vivado/SDK Support | Xilinx devices with 3rd Party Tools | Any other MPSSE based JTAG Tools |
|---|---|---|---|
| TE0790-02 | Yes | Yes | Yes |
| TE0790-02L | No | Yes | Yes |
Table 11: Module variants.
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Technical Specifications
Absolute Maximum Ratings
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
3.3V | -0.3 | 4 | V | FTDI FT2232H data sheet |
| VIO | -0.5 | 3.75 | V | Lattice MachX02 Family data sheet |
| Voltage on pins A - H | -0.5 | 3.75 | V | Lattice MachX02 Family data sheet |
| Storage temperature | -40 | 100 | °C | LED SML-P11 data sheet |
Table 12: Module absolute maximum ratings.
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
3.3V | 2.375 | 3.6 | V | Lattice MachX02 Family data sheet |
| VIO | 1.14 | 3.6 | V | Lattice MachX02 Family data sheet |
| Voltage on pins A - H | 1.14 | 3.6 | V | Lattice MachX02 Family data sheet |
| Operating temperature | -40 | 85 | °C | FTDI FT2232H data sheet |
Table 13: Module recommended operating conditions.
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All dimensions are given in millimeters.
Figure 35: Module physical dimensions drawing.
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Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| - | 01 | prototypes | - | - |
| - | 02 | current available revision | - | TE0790-02 |
Table 14: Module hardware revision history.
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Figure 46: Module hardware revision number.
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Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Ali Naseri | initial document |
Table 15: Document change history.
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