Page History

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Excerpt
PetaLinux SD ETH USB I2C RTC FMeter SI5338 Initialisation with FSBL

Revision History

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Module Model	Board Part Short Name	PCB Revision Support
TE0745-02-30-1I	30	01,02
TE0745-02-35-1C		01,02
		2

Design supports following carriers:

Carrier Model	Notes
---TEB0745

Additional HW Requirements:

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_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter for minimum setup
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project
1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
  Note: Select correct one, see TE Board Part Files
Create HDF and export to prebuilt folder
1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
  Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Create Linux (uboot.elf and image.ub) with exported HDF
1. HDF is exported to "prebuilt\hardware\<short name>"
  Note: HW Export from Vivado GUI create another path as default workspace.
2. Create Linux images on VM, see PetaLinux KICKstart
  1. Use TE Template from /os/petalinux
    Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
Add Linux files (uboot.elf and image.ub) to prebuilt folder
1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
  Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
Generate Programming Files with HSI/SDK
1. Run on Vivado TCL: TE::sw_run_hsi
  Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
  Note: See SDK Projects

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Generate Platform Project or use prebuilt from download
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Launch

Programming

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Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode
Note: See TRM of the Carrier , which is usedand Module.
Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

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Open Serial Console (e.g. putty)
1. Speed: 115200
2. COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
1. User Name: root
2. Password: root

System Design - Vivado

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Block Design

PS Interfaces

Constrains

Basic module constrains

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language	ruby
title	_i_bitgen_common.xdc

You can use Linux shell now.
1. I2C 0 Bus type: i2cdetect -y -r 0
2. RTC check: dmesg | grep rtc
3. ETH0 works with udhcpc
4. USB type "lsusb" or connect USB2.0 device

Vivado HW Manager

SI5338_CLK0 Counter:

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
1. Set radix from VIO signals to unsigned integer.
  Note: Frequency Counter is inaccurate and displayed unit is Hz

SI5338 CLK is configured to 125MHz by default.

System Design - Vivado

Design specific constrain

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language	ruby
title	_i_io.xdc

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For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

Xilinx default FSBL

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design - PetaLinux

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For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

No changes.

U-Boot

No changes.

Device Tree

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
};

Kernel

No changes.

Rootfs

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Block Design

Image Added

PS Interfaces

Type	Note
DDR
QSPI	MIO
ETH0	MIO
USB0	MIO
SD0	MIO
UART0	MIO
I2C0	MIO
GPIO	MIO/EMIO
ETH0 Reset	MIO
USB0 Reset	MIO
I2C0 Reset	MIO
Timer 0	EMIO

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen_common

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

Design specific constrain

No additional constrains.

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

TE modified 2017.2 FSBL

Changes:

Si5338 Configuration see fsbl_hooks.c
Add register_map.h, si5338.c, si5338.h

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design - PetaLinux

HTML
<!-- optional chapter Add "No changes." or "Activate: -->List" -->

For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

No changes.

U-Boot

No changes.

Device Tree

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
};


/* ethernet */
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@1 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <1>;
        } ;
    } ;
};

/* usb */
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};

/* flash */
&flash0 {
    compatible = "micron,n25q256a";
    #size-cells = <1>;
    reg = <0x0>;
    spi-tx-bus-width = <1>;
    spi-rx-bus-width = <4>;
    spi-max-frequency = <10000000>;

};

/* I2C */

&i2c0 {
    #address-cells = <1>;
    #size-cells = <0>;

    rtc0: rtc@6F {
        compatible = "isl12022";
        reg = <0x6F>;
    };


    i2cmux_SFP: i2cmux@72  {
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x72>;

        SFP@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        SFP@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        SFP@2 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        SFP@3 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        SFP@4 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        SFP@5 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        SFP@6 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        SFP@7 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };

};

Kernel

Activate:

USB_ULPI_BUS
RTC_DRV_ISL12022

Rootfs

Activate:

i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

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SI5338

Download ClockBuilder Desktop for SI5338

Install and start ClockBuilder
Select SI5338
Options → Open register map file
Note: File location <design name>/misc/Si5338/RegisterMap.txt
Modify settings
Options → save C code header files
Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 2

New Version 3

Key

Revision History

Launch

Programming

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Vivado HW Manager

System Design - Vivado

Design specific constrain

HTMLFor SDK project creation, follow instructions from:SDK Projects

Application

FSBL

U-Boot

Software Design - PetaLinux

Config

U-Boot

Device Tree

Kernel

Rootfs

Block Design

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - SDK/HSI

Application

FSBL

U-Boot

Software Design - PetaLinux

Config

U-Boot

Device Tree

Kernel

Rootfs

Applications

startup

SI5338

Appx. A: Change History and Legal Notices

HTML

For SDK project creation, follow instructions from:
SDK Projects