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Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1 and JB2:
| VG96 B2B Connector Designator | Count of IO's | Count of LVDS-pairs | Available VCCIO's | Interfaces | Notes | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| JB1 | 7224 single ended | User IO | - | |||||||
| 48 | single ended or 24 differential | User IO | - | |||||||
| JB2 | 54 single ended | User IO | - | |||||||
| 10 single ended or 5 differential | User IO | - | ||||||||
| 2 | I²C | - | ||||||||
| 7 | SD IO | - | ||||||||
| 2 | UART | - | ||||||||
| 6 | USB2.0 | - | ||||||||
| 14 | 1.8V, 2.5V | - | - | JB2 | 64 | 5 | VCCIO_13, VCCIO_33 3.3V | I²C,2x 10/100-BaseT Ethernet, | - | |
| 14 | GbE MDI and SGMII, | - | ||||||||
| 4 | JTAG | The 5 LVDS-pairs on connector JB2 have the prefix 'DISP' in the schematic net names. The I²C, SD IO and the UART interface pins are connected |
Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
VG96 Connector
Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
VG96 Connector
The TEB0729 Carrier Board has soldering pads provides as The TEB0729 Carrier Board has soldering pads provides as place-holders to mount VG96 connectors J8 and J9 to get access the PL-IO-bank's pins and further interfaces of the Zynq SoM. With mounted VG96 connectors, SoM's IO's are available to the user, a large quantity of these I/O's are also usable as LVDS-pairs.
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Following table gives a summary of the pin-assignment, available interfaces and functional IO's of the VG96 connectors J8 and J9:
| VG96 Connector | Count of PL IO's | Count of LVDS-pairs | Interfaces | SoM Control Signals and Interfaces | Notes |
|---|---|---|---|---|---|
| J8 | 72 | 24 | - | - | |
| J9 | 64 | 5 | 'NRST_IN', pin J9-A29 | Drive to ground (Push Button S1, JB3-11 (G) on XMOD header) to reset the SoM. 2) | |
| 'NRST_OUT', pin J9-B30 | Incoming reset signal from SoM's watchdog (implemented on SoM's SC CPLD). 2) | ||||
| 'BOARD_STAT', pin J9-B32 | Frequently flipping signal indicating running SoM. Routed also to XMOD Header, pin JB3-9 (E). | ||||
| 'BOOT_MODE1', pin J9-C31 | Bootmode pin 1, use in conjunction with Bootmode pin 2. | ||||
| 'BOOT_MODE2', pin J9-C32 | Bootmode pin 2, use in conjunction with Bootmode pin 1. | ||||
| I²C, pins J9-A30, J9-A31 | I²C1 interface of module. | ||||
| GbE SGMII, pins J9-A16, J9-A17, J9-A19 J9-A20 | SGMII interface of on-module GbE PHY. |
| VG96 Connector | Count of IO's | Control Signals and Interfaces | Notes |
|---|---|---|---|
| J8 | 24 single ended | User IO | - |
| 48 single ended or 24 differential | User IO | - |
| J9 |
| 54 single ended | User IO | - |
| 10 single ended or 5 differential | User IO | - |
GbE SGMII
| 'NRST_IN', pin J9-A29 |
| I²C | - |
| 'NRST_OUT', pin J9-B30 |
| SD IO | - | |
| 'BOARD_STAT', pin J9-B32 |
| UART | - | |
| 'BOOT_MODE1', pin J9-C31 | USB2.0 | - |
| 'BOOT_MODE2 |
| ', pin J9- |
| C32 | ||
| I²C, pins J9-A30, J9-A31 | 2x 10/100-BaseT Ethernet | - |
| GbE SGMII | GbE MDI and SGMII | - |
| 4 | JTAG | - |
Table 3: General overview of PL I/O signals, SoM's interfaces and control signals connected to the VG96 connectors.
HW-modification Concerning Reset-Signals
12) The pins with the schematic net names 'NRST_IN' (JB2-89) and 'NRST_OUT' (JB2-91) are swapped as part of a HW-modification to rework the Reset-signals of the Carrier-Board in conjunction with the TE0729 SoM.
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| JB3 pin | Signal Schematic Net Name | B2B | Note |
|---|---|---|---|
| C (pin 4) | TCK | JB2-119 | - |
| D (pin 8) | TDO | JB2-117 | - |
| F (pin 10) | TDI | JB2-115 | - |
| H (pin 12) | TMS | JB2-113 | - |
| A (pin 3) | USART0_TX | JB2-96 | - |
| B (pin 7) | USART0_RX | JB2-94 | - |
| E (pin 9) | BOARD_STAT | JB2-112 | also connected to VG96 connector pin J9-B32 |
| G (pin 11) | NRST_IN 3) | JB2-89 | also connected to VG96 connector pin J9-A29 |
Table 12: XMOD header signals and connections. 3) Swapped at HW-Modification with signal 'NRST_OUT' in board-revision 2
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board. Set the DIP-switch with the setting:
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Hardware Revision History
| Date | Revision | Notes | PCN | Schematic Change Notes | Documentation Link | Note |
|---|---|---|---|---|---|---|
| - | 01 | First Production Release | - | - | TEB0729-01 | - |
| - | 02 | Second Production Release | - | Refer to Changes list in Schematic | TEB0729-02 | HW-Modification since 22.08.2017 |
Table 27: Module hardware revision history.
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