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  • Microsemi SmartFusion2 SoC FPGA

  • 8 MByte SDRAM
  • 8 MByte QSPI Flash memory

  • 25 MHz system clock and 32.768 KHz auxiliary clock
  • JTAG and UART over Micro USB connector
  • 1x 3-pin header for Live Probes
  • 1x PMOD header providing 8 GPIOsI/O
  • 2x 14-pin headers (2,54 mm pitch) providing 23 GPIOsI/O

  • 9 user LEDs

  • 1 user push button
  • 3.3V single power supply with on-board voltage regulators
  • Size 61.5 x 25 mm


  1. Microsemi SmartFusion2 FPGA SoC, U5
  2. 8 Mbyte SDRAM 166MHz, U2
  3. Micro USB2 B socket (receptacle), J9
  4. Switch button (reset), S1
  5. Switch button (user), S2
  6. Red LED (user), D10
  7. Green LED (indicating supply voltage), D1
  8. 8x red LEDs (user), D2 - D9
  9. FTDI USB2 to JTAG/UART adapterinterface, U3
  10. 8 Mbyte QSPI Flash memory, U1
  11. 32.768 KHz auxiliary crystal oscillator, Y1
  12. 25 MHz main crystal oscillator, Y2
  13. 1x14 pin header (2.54mm pitch), J2
  14. 1x6 pin header (2.54mm pitch), J4
  15. 3-pin header (2.54mm pitch), J3
  16. 1x14 pin header (2.54mm pitch), J1
  17. 2x6 Pmod connector, J6


Storage device name



Quad SPI Flash (U1) OTP area

DEMO Designempty

SPI Flashempty-
I2C Configuration FTDI EEPROM, U9


FlashPro identification, should not be changed by customer

Table 1: Initial delivery state of programmable devices on the module

Boot Process

By default the configuration mode pins of the FPGA are set to QSPI mode, hence the FPGA is configured from serial Flash memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memoryThere is are no bootmode selection Microchip SmartFusion2 SoC boots always from internal configuration flash, optionally software code for the Cortex-M or soft CPU can be placed to eNVM.

Signals, Interfaces and Pins


BankVCCIOI/O's CountAvailable on ConnectorsNotes
13.3V1456 I/O's connected to FTDI chip, 1 I/O used for user button S2, 2 I/O's connected to red user LEDs D2 and D10.
23.3V37266 I/O's user for QSPI Flash, 5 I/O's connected to red user LEDs D3 ... D7.
33.3V55Bank 3 is dedicated to JTAG interface.
43.3V24022 I/O's are dedicated to live probes, all other I/O's are used as memory interface.
73.3V2222 I/O's available on header J2, 2 I/O's connected to red user LEDs D8 and D9, all other I/O's are used as memory interface.

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is created by the implemented with FTDI FT2232H USB2 to JTAG/UART adapter bridge IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:

JTAG SignalPin on Header J4Note

-can be left open for normal operation

Table 4: optional second JTAG interface or GPIO (JTAGSEL dependent)JTAG header

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:


Table 5: QSPI interface signals

Note: On-board SPI Flash is connected to regular FPGA I/O pins, access to it is only possible when using custom SPI flash IP core or via MSS subsystem SPI when it is connected via fabric to those pins. There is no automatic boot from this flash.

On-board Peripherals

Quad SPI Flash Memory


The TEM0001 FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2.


The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to the bank 1 of the FPGA SoC and are usable for example as UART interfaceFTDI FT2232H Channel A works as JTAG interface compatible to Libero tools. Channel B is connected to FPGA pins with direct access to MSS UART peripheral.

The configuration of FTDI FT2232H chip is pre-programmed on to the EEPROM U9 to make it work as FlashPro5 interface for Libero tools.

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Clock SourceSchematic NameFrequencyClock Input Destination
MEMS Oscillator, U7CLK12M12.0000 MHzFTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin N16

Crystal Oscillator, Y1

-32.768 KHzFPGA SoC U5 auxiliary clock input, pin pins W17/Y17
Quartz Crystal Oscillator, Y2-25.000 MHzFPGA SoC U5 main clock input, pin pins W18/Y18

Table 6: Clock sources overview


ButtonSignal Schematic NameFPGANotes
S1USER_BTNB19user configurable
S2RESETU17system reset (reconfiguration)

Table 8: Push buttons of the module





Page info

Page info
infoTypeCurrent version

Page info
infoTypeModified by

  • update change historyfixed typographical and other mistakes

v.33 Antti Lukats
  • change documentation


v.31Ali Naseri
  • initial release